它内置一个16位高速采样adc、一个内部转换时钟、一个内部基准电压源(和缓冲)、纠错电路，以及串行和并行系统接口端口。
It contains a high speed 16-bit sampling ADC, an internal conversion clock, an internal reference (and buffer), error correction circuits, and both serial and parallel system interface ports.
此外，为了避免高速时序电路中常见的时钟偏差，时钟通道采用负时钟偏差系统，并在时钟树中放置了缓冲器。
Furthermore, in order to avoid clock skew familiar in high-speed sequential logic circuits, negative clock skew system is used in clock routeway and buffers are placed in clock-tree.
文章还对高速电路设计中电源层分配、时钟设计进行了讨论。
The power distribution system and the design of clock also included in this paper.
为了避免高速时序电路中常见的时钟偏差，在时钟树中放置了缓冲器。
In order to avoid clock skew familiar in high-speed sequential logic circuits, buffers are placed in clock-tree.
本文还对高速电路设计中电源层分配、时钟设计进行了讨论。
The power distribution system and the design of clock are also included.
该器件内置一个高速18位采样ADC、一个内部转换时钟、一个内部基准电压缓冲、纠错电路，以及串行和并行系统接口。
The part contains a high-speed 18-bit samplingADC, an internal conversion clock, an internal reference buffer, error correction circuits, and both serial and parallel system interface ports.
更高速率系统的研制目前也在开展中。时钟恢复电路(CRC)是光纤通信和许多类似数字通信领域中不可缺少的关键电路。
Clock recovery circuit (CRC) is the key component in the optical transmission systems as well as in the field of digital transmission.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
由于不匹配的电缆可引起过度的时钟相偏（Clock Skew），导致错误操作，所以相位匹配是有些高速数字电路中特别要注意的事项。
Phase matching is of particular concern with some high speed digital circuits, because unmatched cables may cause excessive clock skew, resulting in erroneous operation.
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