改进算法简化系统结构，降低逻辑设计复杂度，节约了高速存储器部分硬件资源。
This algorithm simplifies the system architecture as well as reduces the complexity of logical design. Moreover it also reduces the hardware resources of high speed memory.
SDRAM是当今一种流行的高速存储器。通过和普通sdram存储器对比，阐述了WISHBONE总线协议下ddr存储器控制器的设计方法和注意事项，并提出一种提高DDR工作效率的预测机制。
This paper based on the mechanism of DDR-SDRAM, gave a way to construct a DDR-SDRAM controller based on WISHBONE bus protocol, and also introduced a forecast method to improve DDR's performance.
这一页存入高速缓冲存储器了。
在你的网络浏览器的高速缓冲存储器里是你最新下载的网络文档。
In your Web browser's cache are the most recent Web files that you have downloaded.
这个示例使用了一个固定大小的高速缓存，如1MB的存储器或100个高速缓存项。
This example USES a fixed size cache, such as 1 MB of storage or 100 cached items.
如果数据或指令没有出现在高速缓存中，或者如果高速缓存线路无效的时候，CPU通过从主存储器中读数据来更新它的高速缓存。
If the data or instruction is not present in the cache, or if the cache line is invalidated, the CPU updates its cache by reading the data from the main memory.
通过把该数据结构的两个元素分离到两条不同的高速缓存线路，一条高速缓存线路的修改就不会导致再次从存储器读入另外一条高速缓存线路。
By separating the two elements of the structure into two different cache lines, modification of one cache line does not cause another cache line to be read in again from the memory.
这个概念围绕一个理念，即基本外壳或基础架构应该提供一些基本需求：电源、联网、管理、一条高速总线、冷却设备、以及存储器。
Well, the concept revolves around the idea that the basic shell or infrastructure should provide the bare necessities: power, networking, management, a high-speed bus, cooling, and storage.
可以在高速缓冲存储器策略中使用这个信息头来构建ID，而不必解析soap消息。
This header can be used in a cache policy to build IDs without having to parse the SOAP message.
然后，可以使用cache - id从高速缓冲存储器中检索服务响应信息来使性能最优化。
The cache-id can then be used to retrieve service response information from the cache to optimize performance.
后备存储器通常是一个高速磁盘。
光分组交换由于缺乏高速光逻辑器件、光缓冲存储器等，因此还处于研究阶段。
OPS still is placed in to study the stage because of lacking of the high-speed optical logic device and optical buffer.
对提高高速数据采集系统的采样率和存储器带宽这两大技术难题提出了补救措施。
The compensating measure is put forward to solve the two technological problems of sampling and memory bandwidth enhancement of high speed data acquisition systems.
采用高速A／D转换器以及帧存储器提高系统的存取速度。
Speed is increased by using high speed A/D convertor and frame memorizer.
有一个颇受欢迎的解决办法是在微处理器内部放置一个叫高速缓冲内存储器的小内存。
One popular aid is to place a small memory, called a cache, right on the microprocessor itself.
金属纳米晶存储器件具有低功耗、高速读写特性及较高的可靠性，因此近年来在非易失存储器研究领域备受关注。
In recent years, in the field of non-volatile memory research, metal nanocrystal memory with low-power, high-speed read and write characteristics and high reliability receives much attention.
此系统主要由单片机，USB主机控制器，高速RAM,FLASH存储器等器件组成，使得数码摄像头在嵌入式领域应用成为现实。
This system, which facilitates the utility of PC cameras in embedded application, is composed of MCU, USB Host Controller, high-speed RAM and FLASH memory.
该系统采用DSP与PC构成主从式并行结构，共享存储器实现双机高速数据通信。
In this system the master-slave parallel structure is composed by DSP and PC. The dual machine high speed communication is implemented by the Shared memory.
在高速网络中，商用存储器的存取速率一直是路由器调度性能提高的制约因素。
The commercially available memory rate can hardly keep up with the requirement of building high speed routers since the transmission capacity of the network is greatly improved.
随机存储器缓存是由高速静态随机存储器组成的存储器的一部分。
RAM cache is a portion of memory made of high- speed static RAM.
该系统能发挥两种微机的优势，利用总线周期窃用和分散型共享存储器技术，实现紧耦合方式的高速通信。
The system takes advantage of both, computers and can realize high rate communication in tight coupling style, by using bus period stealing and distributional memory sharing.
由此，能够在不导致成本增高的情况下高速地进行针对存储器的初始化处 理。
This makes it possible to carry out an initialization process with respect to the memory at a high speed, without causing an increase in cost.
为了解决数据量庞大、高速数据存取的问题，本文采用了FPGA芯片和同步动态存储器(SDRAM)来实现矩阵转置运算。
For the problem of huge data storage, use SDRAM to store the data, and use FPGA to control SDRAM to complete the transpose.
采用位线平衡技术、高速两级敏感放大器及可预置电压的数据输出缓冲，以提高存储器的读写频率。
A fast access time is obtained by utilizing a bit line equalizing technique, a high speed hierarchical sense amplifier and a preset data output buffer.
同时提供高密度存储器的小尺寸，这一解决方案还保持高速传输与低噪声干扰，因而成为理想的选择移动市场。
While providing high-density memory with small footprint, this solution also maintains high speed transmission with low noise interference which becomes an ideal choice for mobile market segment.
目标处理器能够比访问系统存储器中的数据更有效率地访问高速缓存中的数据。
The target processor can access data in the cache more efficiently than it accesses data in the system memory.
在此前提下，采用高速数据传输技术成为必然，DMA(直接存储器访问)技术就是较理想的解决方案之一，能够满足信息处理实时性和准确性的要求。
DMA (Direct Memory Access) technology is one of the best solutions which could meet the requirements of real-time and accuracy for information processing.
成功实现了用高密度、相对低速的FLASH存储器对高速实时数据的可靠存储。
By using of the storage board, high speed real-time data can be successfully stored with high density lower speed FLASH chips.
成功实现了用高密度、相对低速的FLASH存储器对高速实时数据的可靠存储。
By using of the storage board, high speed real-time data can be successfully stored with high density lower speed FLASH chips.
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