人们常说，高电平的负反馈引起了低旋转率。
It is often said that high levels of NFB enforce a low slew-rate.
其余的都是高电平。
每个解码输出在一个全时钟周期内保持高电平。
在所有故障安全条件下，接收器输出为高电平。
The receiver output will be HIGH for all fail-safe conditions.
总线空闲时，两条线都是高电平(集电极开路)。
The bus is "idle" when both lines are high (open-collector).
高电平有效复位。
逻辑信号从高电平到低电平的转换被称为下降沿。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
在这种模式下，TX信号为高电平期间将重置或空闲。
In this mode, the TX signal will be HIGH during reset or idle.
因此，当时钟变为高电平时，IC2产生一个计数输出。
Therefore, when the clock goes high, IC2 produces an output count.
此输出缓冲器可快速地将输出电压切换为低电平和高电平。
The output buffer has ability of switching the output voltage to be low level and high level in high-speed.
通常，在数字信号处于逻辑高电平状态时，脉冲指时间周期。
Typically, a pulse refers to a period of time when a digital signal is in a logic high state.
如果一个标志是要传输时，输出变为高电平后，在时钟的上升沿。
If a mark is to be transmitted, the output goes high after the rising edge of the clock.
为了防止现代的高电平输出，可使用RT100替代调制解调器。
In cases of high modem output levels (or inability to lock) the modem can be replaced by the RT100.
单片机通过测量输入脉冲的高电平时间及周期而实现占空比测量。
The time of high level and the cycle for input pulse was measured with micro-controller to calculate duty cycles.
变为高电平，然后立即变为低电平，这表示从设备芯片已经装备好。
Thefirst time CSn goes low, MISO goes high and then low again immediately, indicating that the chip is ready.
交流供电的源通常具有很高电平的电源频率共模电压(常常有几伏)。
An AC powered source usually has a significant level (often several volts) of line frequency common mode voltage.
应用概率统计原理导出了天线副瓣最高电平和天线增益损失的估计公式。
With the help of statistic principle, the estimation formulas of the peak sidelobe level and gain loss are derived.
接收器输入具有失效保护特性，当输入开路时，可确保逻辑高电平输出。
The receiver input has a fail-safe feature that guarantees a logic-high output if the input is open circuit.
如果输入信号电平超过可编程阈值，粗调阈值上限指示器就会变为高电平。
If the input signal level exceeds the programmable threshold, the coarse upper threshold indicator goes high.
在+5V和每根线之间连接着一个电阻，所以总线的空闲状态是高电平。
A resistor is connected between each line and + 5v, so the idle state of the bus is high.
当键盘或者鼠标想发送数据时，它首先必须检查时钟线，确认它处于高电平。
When the keyboard or mouse wants to send information, it first checks the Clock line to make sure it's at a high logic level.
高电平装置为原音响系统提供高保真的效果，并最大限度地重现原有的音质。
High Level interfaces, These provide a high fidelity connection capability with the original sound system in your car, giving you all the original features with great Genesis sound quality.
随后，在预先设定的有效延时时间后，其从低电平有效复位回到高电平状态。
Subsequently, after a predetermined time-out-active period, it goes back to the high state in an active-low reset.
这两个器件决定Q 1什么时候导通，从而为输出提供保持时间可调的高电平。
These two components determine when Q1 turns on and thus provide an adjustable hold time for the output to hold high.
一个有两个工作状态的电路或设备处于高电平状态或经常活动状态的时间百分比。
The percentage of time that a circuit or device with two operational states is in the higher level or more active state.
在水下焊接过程中，脉冲电源输出高电平时，停止送丝，电弧稳定燃烧并形成熔滴；
During the welding process, when underwater welding power outputs high level, the system stops feeding wires and wires burn upwards with forming molten droplets.
当设置到高电平逻辑（电路）时，两个扩音器都无声，处于低耗能（闲置）状态；当…
When set to logic high, both amplifiers are muted and in low power (…
本发明可根据自动测试设备的指令维持一条或多条测试数据线在一定时间内的高电平状态。
The system can maintain one or a plurality of test data wires in the high level state in certain time according to the instructions of the automatic test equipments.
本发明可根据自动测试设备的指令维持一条或多条测试数据线在一定时间内的高电平状态。
The system can maintain one or a plurality of test data wires in the high level state in certain time according to the instructions of the automatic test equipments.
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