• 使用VHDL语言设计LCD驱动时序电路

    To design the timing circuit of LCD using VHDL.

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  • 利用CPLD复杂可编程逻辑器件,结合VHDL硬件描述语言,设计线阵CCD驱动时序电路

    Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.

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  • 介绍了转移型面紫外CCD—CCD180—512-SFT在对驱动时序进行分析的基础上,设计了驱动时序电路完成仿真

    One of frame transfer array UV-CCD—CCD180-512-SFT was introduced. According to its driving schedule, the driving scedule circuit was designed and the system simulation has been successfully fulfilled.

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  • 解决了CCD时序电路功率驱动电路设计问题。

    The paper designs the circuits of working clock and power driver for CCD.

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  • MCNC标准单元测试电路中组合时序电路实验结果显示电路经过时延驱动优化布局最大路径时延最多减少了31%。

    MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.

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  • MCNC标准单元测试电路中组合时序电路实验结果显示电路经过时延驱动优化布局最大路径时延最多减少了31%。

    MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.

    youdao

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