并使用VHDL语言设计LCD驱动时序电路。
利用CPLD复杂可编程逻辑器件,结合VHDL硬件描述语言,设计了一种线阵CCD驱动时序电路。
Use CPLD and VHDL together to design the time sequence driving circuit for a kind of linear CCD.
介绍了一种帧转移型面阵紫外CCD—CCD180—512-SFT,在对它的驱动时序进行分析的基础上,设计了驱动时序电路并完成了仿真。
One of frame transfer array UV-CCD—CCD180-512-SFT was introduced. According to its driving schedule, the driving scedule circuit was designed and the system simulation has been successfully fulfilled.
解决了CCD的时序电路及功率驱动电路设计问题。
The paper designs the circuits of working clock and power driver for CCD.
对MCNC标准单元测试电路中组合和时序电路的实验结果显示, 电路经过时延驱动优化布局后的最大路径时延最多减少了31%。
MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.
对MCNC标准单元测试电路中组合和时序电路的实验结果显示, 电路经过时延驱动优化布局后的最大路径时延最多减少了31%。
MCNC(microelectronics centre of north-carolina) standard cell benchmarks are experimented and the results show that the algorithm can make the longest path delay improvement up to 31%.
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