一种双环路频率综合器及其相位噪声分析方法。
The invention relates to a double-loop frequency synthesizer and a phase noise analyzing method.
提出了一种应用于频率综合器的全差分电荷泵电路。
A fully differential charge pump for a frequency synthesizer is proposed.
给出了一种基于DDS驱动PLL的频率综合器结构。
DDS-driven PLL frequency synthesizer architecture is given in this paper.
本文介绍了应用在单芯片FM接收系统中可变带宽频率综合器的设计。
This paper presents a design of Adaptive-Bandwidth Frequency Synthesizers used in single chip FM receiver system.
该频率综合器采用模拟调谐和数字调谐相结合的技术来提高相位噪声性能。
A combined tuning technique of digital tuning and analog tuning is used to improve the phase noise of frequency synthesizer by decreasing the gain of VCO.
现代无线通信要求频率综合器同时满足快速切换时间，小信道宽度和低噪声性能三方面的要求。
Modern wireless communication requires that the frequency synthesizer should have fast settling time, small channel width and low phase noise.
介绍一种低相噪、捷变频x波段频率综合器设计方法，并进行理论分析、计算，最后给出测试结果。
A design method for low phase noise agile X-band frequency synthesizer is presented, the theoretic analysis and calculation is performed and the test results are given.
仿真结果表明，该锁相环频率综合器达到了设计指标，可以应用于两次变频的“宽带中频”集成接收机。
The simulation results show that the designed PLL frequency synthesizer meets the design specification and it can be used in the integrated wideband if with double conversion wireless RF receiver.
频率综合器是SRD收发器的关键模块，本文主要工作是研究与设计应用于SRD收发器的频率综合器。
Frequency synthesizer is the key block of SRD transceivers, and this thesis concentrates on the research and design of frequency synthesizers for SRD applications.
针对电流型电荷泵PLL频率综合器芯片，提出一种称为极值相位裕量的无源环路滤波器方案和设计方法。
A passive loop filter scheme and the design method of the filter for current charge pump PLL frequency synthesizer chip are given in the paper.
小型化是现代电子通信系统的一个重要的研究方向，射频信道的小型化设计重点是频率综合器的小型化设计。
Miniaturization is an important research direction in modern electronic communication system, and the design of RF channel emphasizes the miniaturization design of frequency synthesizer.
本发明公开了一种双环路频率综合器及其粗调环路的调谐方法，属于无线收发机中的 频率综合器技术领域。
The invention discloses a dual-loop frequency synthesizer and a tuning method of rough adjustment loop thereof, belonging to the field of frequency synthesizer in wireless transceiver.
由于锁相环电路具有的窄带、跟踪、滤波等优点，因此在现有的雷达系统中，普遍采用由锁相环构成的频率综合器。
Frequency synthesizer composed of PLL is widely used in radar system because of PLL specialties such as narrow band, signal tracking and filter.
这种方法基于频率综合器的频域模型，能比较准确地预测分频器的相位噪声和它对整个频率综合器相位噪声的影响。
Based on the frequency-domain model of synthesizer, the method can accurately predict the phase noise of the divider and its influence to the phase noise of synthesizer.
介绍了一种应用直接数字频率综合器（DDS）技术，基于可编程逻辑器件（CPLD）和单片机设计的低频信号源。
According to the technology of direct digital synthesis(DDS), a kind of low frequence signal source was introduced based on the Complex Programmed Logical Device(CPLD)and Single Chip Micyoco(SCM).
介绍低相噪NPLL频率综合器的设计及实验结果。提出用无源环路滤波器比用有源环路滤波器更好，可获得低相噪设计。
This paper gives the design and experimental results of low noise NPLL frequency synthesizer and concludes that the passive loop filter is more suitable for low noise design than active loop filter.
提出了一种间接合成的低相位噪声频率综合器的设计，该频综器用于某机载雷达中，从而要求其在极其恶劣的环境中同样具有良好的性能。
This paper presents a low phase noise indirect frequency synthesizer, which used in airborne fire control radar and is required to operate in a very harsh environment.
它通过综合ads - B状态向量、飞行器目标和其它信息，来减少非必要的警报频率。
It will also reducing unnecessary alarm rate by incorporating the ADS-B state vector, aircraft intent, and other information.
提出一种对水轮发电机组水压频率进行综合调节的记忆递归网络灵敏度预测控制器。
A sensitivity predictive controller with memory recurrent network for use in the comprehensive control of the water hammer and the frequency is proposed.
目的：观察合并冠心病心绞痛的病态窦房结综合征患者置入频率应答起搏器（DDDR）的临床疗效及运动耐量评价。
Objective: To observe the clinical effect and evaluate the exercise tolerance in sick sinus symptom patients with angina pectoris after implanting rate responsive pacemaker (DDDR).
为了提高综合频率，本文提出了对滤波处理单元的改进，采用流水线输入的竖直滤波器和改进的2级对角滤波器可以大大缩短导致的延时路径。
To improve the synthesis frequency, changes are made to the filter processing element. With pipelined vertical FIR and revised 2-level diagonal FIR, the corresponding delay path can be shortened.
为了提高综合频率，本文提出了对滤波处理单元的改进，采用流水线输入的竖直滤波器和改进的2级对角滤波器可以大大缩短导致的延时路径。
To improve the synthesis frequency, changes are made to the filter processing element. With pipelined vertical FIR and revised 2-level diagonal FIR, the corresponding delay path can be shortened.
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