该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术，保证了芯片的高性能和速度，节省了芯片面积。
A modified direct digital frequency synthesis (DDS), pipelined structure, and time-sharing ROM are adopted in the chip, for saving chip area and ensuring high performance and speed.
该芯片采用了改进的直接数字频率合成算法、流水线结构与ROM分时复用技术，保证了芯片的高性能和速度，节省了芯片面积。
A modified direct digital frequency synthesis (DDS), pipelined structure, and time-sharing ROM are adopted in the chip, for saving chip area and ensuring high performance and speed.
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