该时钟板基于频率合成器来产生高精度、高稳定度、低抖动的时钟，用于高速高精度背板测试平台。
The system based on the frequency synthesizer can offer a high accuracy, high stability and low jitter clock for a high speed and high precision backplane test platform.
提出了一种展频时钟生成的方法，使用MATLAB和SIMULINK开发出了快速模拟基于分数N型频率合成器的展频时钟生成器的环境。
A fast simulation environment has been developed using MATLAB and SIMULINK for behavioral level simulation of spread spectrum clock generator based Fractional-N frequency synthesizers.
利用直接频率合成技术产生高精度、高稳定度的扩频伪码时钟。
The direct digital synthesis (DDS) is adopted to generate the pseudo-random code clock having high precision and stability.
提出基于频相的直接数字频率合成技术（DDFS）实现采样的跟随时钟。
Offering direct digital frequency synthesis (DDFS) based on the frequency -phase to achieve the following sampling clock.
提出基于频相的直接数字频率合成技术（DDFS）实现采样的跟随时钟。
Offering direct digital frequency synthesis (DDFS) based on the frequency -phase to achieve the following sampling clock.
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