随着集成电路设计的规模变得越来越大、功能越来越复杂，功能验证已经成为设计流程的主要瓶颈。
Since integrated circuit designs are becoming more and more complex, functional validation has been the main bottleneck of the design flow.
验证是当前越来越复杂的集成电路设计中的瓶颈，在寄存器传输级（RTL）直接做验证是目前比较有效的一种途径。
Verification is the bottleneck of more and more complex integrated circuit designs, and doing verification directly on register transfer level (RTL) is a promising solution.
在芯片规模指数式上升和要求面市时间快速缩短的双重压力下，验证已成为数字集成电路设计的瓶颈。
Under pressure of the increase of chip scale and the decrease of timing to market, verification has become the bottleneck of digital IC design.
芯片验证，尤其是功能验证已成为当前集成电路设计中最困难、最具挑战的课题之一。
Chip verification, especially functional verification has become one of the most difficult and challenging issues in IC design.
芯片验证，尤其是功能验证已成为当前集成电路设计中最困难、最具挑战的课题之一。
Chip verification, especially functional verification has become one of the most difficult and challenging issues in IC design.
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