我们再也不能如同处理低速设计一般，视互连为集总电容或简单的延迟线。
It is no longer possible to model interconnects as lumped capacitors or simple delay lines, as could be done on slower designs.
我们再也不能如同处理低速设计一般，视互连为集总电容或简单的延迟线。
It is no longer possible to model interconnects as lumped capacitors or simple delay lines, as could be done on slower designs.
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