这已被设计与Intersil的高频双极电介质隔离工艺构造和特点，从一个以前从未真正差速器可用的动态参数。
It has been designed and constructed with the Intersil High Frequency Bipolar Dielectric Isolation process and features dynamic parameters never before available from a truly differential device.
采用平面选择注入隔离工艺制作MESFET及旁栅电极，通过改变半导体特性测试仪的延迟时间参数，深入研究了不同沟道电流的数据采集时间对旁栅效应迟滞现象的影响。
The influence of different data collection time of channel current on the side gating hysteresis effect is studied by changing the delay time of semiconductor characteristic testing set.
采用平面选择注入隔离工艺制作MESFET及旁栅电极，通过改变半导体特性测试仪的延迟时间参数，深入研究了不同沟道电流的数据采集时间对旁栅效应迟滞现象的影响。
The influence of different data collection time of channel current on the side gating hysteresis effect is studied by changing the delay time of semiconductor characteristic testing set.
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