为提高除法计算的速度，提出了新的基-16算法的高速除法器算法，并以专用集成电路设计方法实现。
In order to improve the speed of division, a novel algorithm of radix-16 high speed divider and its ASIC implementation are presented.
在8块AN221E04芯片中实现模拟乘法器、求小求和以及除法等单元电路，由各单元电路组合成完整的控制器。
All cell circuits such as analog multiplier, seeking small and sum, divider were implemented on 8 AN221E04s, and then an intact controller was assembled with the cell circuits.
采用数字移位器替代传统的除法器，使得电路结构大大简化，而且在很大的倍频系数范围内都保持很好的稳定性。
Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes.
采用数字移位器替代传统的除法器，使得电路结构大大简化，而且在很大的倍频系数范围内都保持很好的稳定性。
Use a binary digital shifter replace the traditional divider in ADPLL, make the structure simple and keeps the loop gain constant when the frequency multiplication factor changes.
应用推荐