此门阵列采用的BFL预功能级标准逻辑单元，具有九种组合逻辑功能及两种不同选择的驱动能力，并具有输出电平调节功能。
The pre-functional cell of standard buffered FET logic (BFL) adopted by the gate array possesses nine logic functions, two different kinds of driving capabilities, and the level control ability.
在此基础上，采用高速数字信号处理器、大规模可编程逻辑门阵列和实时软件进行系统设计，完成了原理样机的研制。
On this basis, the principle prototype is developed with high speed digital signal processor (DSP), the huge reprogrammable logic gate arrays (FPGA) and real-time software.
可编程逻辑，特别是现场可编程门阵列(FPGA)便是这样的解决方案。
Programmable logic, in particular field programmable gate array (FPGA) is such a solution.
该驱动板以现场可编程逻辑门阵列为DSP与编码器、脉冲命令和功率模块等电路之间的接口，以最新的智能功率模块(IPM)作为功率输出驱动芯片。
FPGA is used as interface between the DSP and the encoder, pulse command and power module. The latest intelligent power module (IPM) is used to provide the function of power stage.
该驱动板以现场可编程逻辑门阵列为DSP与编码器、脉冲命令和功率模块等电路之间的接口，以最新的智能功率模块(IPM)作为功率输出驱动芯片。
FPGA is used as interface between the DSP and the encoder, pulse command and power module. The latest intelligent power module (IPM) is used to provide the function of power stage.
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