采样保持电路、电压源电路设计。
完整解决方案：基准电压源和采样保持器。
介绍一种用于流水线adc的采样保持电路。
Introduction sampling-hold circuit of a pipeline used for ADC.
设计了一个用于流水线型模数转换器的低压采样保持电路。
A low supply voltage sample-and-hold circuit for a pipelined analog-to-digital converter is described.
该器件的两个输入采样保持放大器之间具备高匹配度的孔径延迟。
The part features very tight aperture delay matching between the two input sample and hold amplifiers.
模拟输入电路包含模拟多路复用器，仪表放大器，以及采样保持电路。
The analog input circuitry contains the analog multiplexer, the instrumentation amplifier, and the sample-and-hold circuitry.
采样速度和保持精度，是采样保持电路设计制作者最为关注的两项指标。
Sampling rate and holding accuracy are two most concerned targets in designing the sample-and-hold circuit.
包括模拟电路和数字电路，模拟电路由运算电路、采样保持电路、防饱和电路组成；
The including imitates the telephone and digital circuits, the simulation telephone is from the operation telephone, sample the hold circuit and defend the saturated telephone constitutive enzyme;
在分析磁通门常用背景磁场补偿方法基础上，提出一种新的采样保持电路自动补偿方法。
On the basis of analyzing the common methods of background magnetic field compensation, a new automatic compensation method based on sample and hold circuit is put forward.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。
Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges.
每个ADC均具有宽带宽、差分采样保持模拟输入放大器，支持用户可选的各种输入范围。
Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges.
这是一款完整的单芯片adc，内置片内高性能、低噪声采样保持放大器和可编程基准电压源。
It is a complete, monolithic ADC with an on-chip, high performance, low noise sample-and-hold amplifier and programmable voltage reference.
该电路的模拟部分包括电荷放大器、后级放大电器、相关双取样与采样保持电路、积分器、单位增益缓冲器。
The analog part includes self-test circuit, charge amplifier, post-amplifier circuit, CDS and S/H circuit, integrator, unity gain buffer.
流水线ADC的模块有采样保持电路、乘法数模转换器、子ADC、数字校正电路、时钟产生电路和时间对齐电路。
The whole circuit consists of Sample and Hold Circuit, the Multiplicative A/D Converter, the Sub-ADC, the Digital Calibration Circuit, the Clock Generator and the Time Synchronizer.
但当逐次比较式adc的采样频率过高时，会使其内部采样保持的开关电容充电不充分，从而导致ADC转换误差过大。
But when the sampling frequency of successive-approximation ADC is too high, the switched capacitor can't be charged properly. And this will result in too big conversion error.
通过电压峰值采样保持电路对IGBT串联二极管反压值进行采样，后经DSP A/D转换模块与反压设定值进行比较。
Sample the negative voltage on the diode series with IGBT by Peak hold switch circuit, and cut-in A/D module in the DSP, compared with setting value.
采样保持电路设计采用了电容下极板采样技术，不仅有效地避免了电荷注入效应引起的采样信号失真，而且消除了时钟馈通效应的不良影响。
The sample and hold circuit is employed by the bottom plate sampling technique, which could not only cancel the charge injection error but also eliminate the effect of clock feed-through.
AD 9446是一款16位单芯片采样模数转换器(adc)，内置一个片内采样保持电路，专门针对高性能、小尺寸和易用性进行了优化。
The AD9446 is a 16-bit, monolithic, sampling analog-to-digital converter (ADC) with an on-chip track-and-hold circuit. It is optimized for performance, small size, and ease of use.
检测电路分为全桥平衡模块、电荷放大器模块、信号放大模块、相关双采样模块、采样保持模块、闭环反馈模块、低通滤波模块和数字时序控制模块。
The circuit is divided into full bridge module, charge sense amplifier module, correlated double sampling and holding module, closed-loop feedback module, low-pass filter and time controlling module.
AD9218 功能框图AD9218是一款双核10位单芯片采样模数转换器（ADC），内置片内采样保持电路，具有低成本、低功耗、小尺寸和易于使用等特性。
The AD9218 is a dual 10-bit monolithic sampling analog-to-digital converter with on-chip track-and-hold circuits. The product is low cost, low power, and is small and easy to use.
为了保持控制系统的正常工作，传感器的采样与控制必须按照一定的周期间隔。
For the control system to work, sensor sampling and control must be performed at periodic intervals.
其先进的电流检测电路采用采样和保持方法，以提供精确的平均电流信号。
Its advanced current sensing circuitry employs sample and hold methods to provide a precise average current signal.
它们价格适宜，您能在看到长时间周期的同时保持高采样率，从而了解所设。
They give you an affordable way to see long time periods while maintaining high sample rate so you can see details in your designs.
为了保持样品沉积物的层次结构，就要用空心铁管采样器。
To take samples that retain the larger structure of the sediment, a core sampler is used.
深存储器意味即在捕获长的时间周期时仍能保持高采样率。
Deep memory means that the sample rate stays high even when capturing long time periods.
设计了以C8051F 060混合信号微控制器为核心的全数字信号检测系统，实现其采样信号和调制信号的相位关系保持。
An all digital signal detecting system using C8051F060 as its core was completed. It can maintain the phase relation of sampling signal and modulating signal.
通过实验，重采样后的模型能够和原有模型保持几何信息一致。
After our up-sampling, the model holds the same geometry as the original model.
通过采用比率采样技术，在保持元件性能不变的前提下，可提高测量精度。
By using the ratio sampling technology, the measurement accuracy can be improved to the extent that the performance of components is kept unchanged.
针对这类非周期异步多速率系统分析、设计困难这一问题，研究了其闭环系统性能关于采样器、保持器时间延迟的连续性问题。
Aiming at the difficulties in analyzing and designing this kind of asynchronous systems, we investigate the continuity property of its' close loop performance on the time delay of sampler and hold.
深海微生物取样器的关键技术在于如何保持高压采样筒体的压力——6小时的压力变化不超过10%。
The key technique of the sampling machine lies in how to keep the pressure variety of the pressure-6 hours of the high pressure sample tube body not over 10%.
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