MOS逻辑门电路的功率损耗与其门电路的输出翻转成正比。
Heat dissipation in MOS gate is in direct Proportion to its output switching activity.
数字逻辑门电路作为集成电路被制造：所有组成的晶体管和电阻建立在一块半导体材料上。
Digital logic gate circuits are manufactured as integrated circuits: all the constituent transistors and resistors built on a single piece of semiconductor material.
在硅晶片的表面将它们连接起来，就形成了逻辑门电路，这就是计算机，手机，电视机以及其它电子产品中最基础的元件。
Linked together on the surfaces of silicon chips, they form the logic gates that do the calculations in computers, mobile phones, television sets and other electronic gadgets.
在逻辑门电路测试技术中，可以在泛序测试法基础上建立故障诊断树，用于完成单电路故障的检测与定位诊断。
In the technologys of logic circuit test, we can use diagnosis tree to finish the test of logic element fault.
电子组件——四千个晶体管组成的逻辑门电路所形成的微处理器核心——使用并五苯材料制成，这是一种易弯曲的有机材料，能作为某种半导体使用。
The electronic components-4, 000 transistors organised into the logic gates that form the core of a microprocessor-are made of pentacene, a flexible organic material that can act as a semiconductor.
电子组件——四千个晶体管组成的逻辑门电路所形成的微处理器核心——使用并五苯材料制成，这是一种易弯曲的有机材料，能作为某种半导体使用。
The electronic components-4,000 transistors organised into the logic gates that form the core of a microprocessor-are made of pentacene, a flexible organic material that can act as a semiconductor.
分析了CMOS逻辑门电路在运行时的电流特征，阐明了集成电路中数据与电磁辐射的相关性，建立了寄存器级电磁信息泄漏汉明距离模型。
The result shows that EM information leakage exists in CMOS integrated circuit during work, XOR operation in each round of DES is an attack point.
本文介绍了该逻辑学和其在计算纳米级门电路的概率分布方面的应用。
This paper describes the logics and the using in computing the probability distribution of the nano-gate states.
提出了一种建立数字门电路宏模型的方法 ，采用该方法建立的门电路宏模型可以对门电路以及由门电路构成的数字电路进行逻辑仿真 。
The said digital gate circuit macro model can be used to perform a logical simulation for gate circurit and the digital circuit formed by the gate circuit.
介绍以中规模集成计数器为核心，结合中规模集成组合逻辑器件及少量门电路进行时序逻辑电路设计的方法。
This paper introduces one way to design scheduling logic circuit with medium-scale integrated counter at the core and based on MSI.
本文提出了一种建立数字门电路宏模型的方法，采用该方法建立的门电路宏模型可以对门电路，以及由门电路构成的数字电路进行逻辑仿真。
The said digital gate circuit Marco model can be used to perform a logical simulation for gate circuit and the digital circuit formed by the gate circuit.
论证了用这些门电路所构成的二值逻辑系统对所有向中型故障是完全自校验的。而对无中型故障，该系统是易于测试的。
It is proven that the binary logic system realized with these gates is totally self-checking for mid-seeking faults.
本文对于多值逻辑代数系统中的基本运算和实现这些基本运算的门电路，作了必要的阐述。
This paper gives a necessary introduction to the base operation of the multi-valued logic algebra system and fundamental gate circuit for realizing these base operation.
这类门电路可以用于构成四值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用。
This kind of gate circuit can be used in forming 4 value combination logic circuit and order part logic circuit, it also can be combined with DYL series circuits.
这类门电路可以用于构成四值组合逻辑电路和时序逻辑电路，也可以和DYL系列电路配合使用。
This kind of gate circuit can be used in forming 4 value combination logic circuit and order part logic circuit, it also can be combined with DYL series circuits.
应用推荐