而当在单独的内存段中创建F CM缓冲区时，在同一物理节点上的不同逻辑分区的FCM守护进程间的通信将通过共享存储器进行。
When the FCM buffers are created in a separate memory segment, the communication between FCM daemons of different logical partitions on the same physical node occurs through Shared memory.
分页空间（或交换空间）是一种逻辑卷，用来存储不使用随机存取存储器（RAM）进程的临时区域。
Paging space, or swap space, is a type of logical volume that serves as a staging area for processes that are not using active random-access memory (RAM).
就磁盘而言，Linux逻辑分区支持三种不同的存储器选项。
In the case of disks, Linux logical partitions support three different storage options.
存储器则是由10个硬盘驱动器(每个硬盘容量为698GB； 7,200转数)组成，由一个硬盘控制器组织成一个逻辑卷(RAID5)。
The storage consisted of 10 hard drives (698 GB each; 7,200 RPM), organized as a single logical volume (RAID 5) using a hardware controller.
程序存储器的导址逻辑是由寄存器来实现的，这个寄存器叫程序计数器。
This program memory addressing logic is handled by a register referred to as a program counter.
逻辑分析仪：添加了16个集成的深存储器数字通道，可显示关键的数据值和时间关系。选择MSO 9404a。
Logic analyzer: 16 integrated deep memory digital channels are added, which can display the key data and time. Select MSO9404A.
光分组交换由于缺乏高速光逻辑器件、光缓冲存储器等，因此还处于研究阶段。
OPS still is placed in to study the stage because of lacking of the high-speed optical logic device and optical buffer.
缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
BIST控制器不仅可以执行传统的存储器测试算法，而且可以生成用于逻辑模块的测试向量。
The BIST controller can not only perform traditional memory test algorithms but also generates test patterns required for the logic part.
泰瑞达是引领全球逻辑、RF、模拟、电源、混合信号、存储器技术的自动测试设备供应商。
Teradyne is a leading worldwide supplier of automatic test equipment for logic, RF, analog, power, mixed-signal, and memory technologies.
研究了系统的程序指令集、逻辑堆栈和I/O存储器数据类型，实验表明系统具有良好的实时性和可靠性。
Program instruction set, logic stack and data type of I/O memory which are tied up with tasks in the soft-PLC system are analyzed and studied.
针对以上问题，本文在研究已有建库技术的基础上，针对存储器的逻辑参数提取提出新的解决方案。
Faced with these problems, this paper presents new methods for parameter extraction of memory on the base of current research about library building technology.
数据总线上的输入数据是否写入存储器，取决于此时的DM的输入逻辑。
Input data appearing on the data bus, is written to the memory array subject to the DM input logic level appearing coincident with the data.
逻辑分析仪：16个快速的深存储器数字通道让您看到关键的数值和定时关系。
Logic analyzer: 16 fast deep memory digital channels allow you to see key numerical and timing relationships.
逻辑分析仪：添加了16个集成的深存储器数字通道，可显示关键的数据值和时间关系。
Logic analyzer: 16 integrated deep memory digital channels are added, which can display the key data and time.
文中的设计思想和具体的逻辑电路可以通用于所有先进先出存储器的设计。
In this paper, we discuss a FIFO memory electrocircuit, which is designed from the top down and have been fabricated successfully.
本发明提供了电源电平升高的可编程逻辑器件存储器单元。
Programmable logic device memory elements with elevated power supply levels are provided.
它的根本的外部运作，是从一开端就一些详细问题，来处理内存逻辑的，如顺序存储器末端。
Its basic internal operation is to solve logic from the beginning of memory to some specified point, such as end of memory or end of program.
在数据加载操作过程中，可以按与可编程核心逻辑电源电压相等的电源电压对存储器单元供电。
During data loading operations, the memory elements may be powered with a power supply voltage equal to the programmable core logic power supply voltage.
计算机包括五个基本部分：输入设备、存储器、算术逻辑运算器、控制器和输出设备。
The computers contains 5 basic sections:input , memory, arithmetic and logic, control, and output.
在正常操作过程中，可以按比可编程核心逻辑电源电压高的电源电压对存储器单元供电。
During normal operation the memory elements may be powered with a power supply voltage that is larger than the programmable core logic power supply voltage.
随后，处理逻辑通过查找虚拟本地存储器地址所表示的物理地址来处理存取请求(处理框602)。
Next, processing logic processes the access request by looking up the physical address represented by the virtual local memory address (processing block 602).
改进算法简化系统结构，降低逻辑设计复杂度，节约了高速存储器部分硬件资源。
This algorithm simplifies the system architecture as well as reduces the complexity of logical design. Moreover it also reduces the hardware resources of high speed memory.
当阈值电压为负且通过向控制栅极施加0V来尝试读取时，存储器元件将接通以指示正在存储逻辑1。
When the threshold voltage is negative and a read is attempted by applying 0 V to the control gate, the memory element will turn on to indicate logic one is being stored.
系统以ARM微处理器和FIFO存储器为核心，利用可编程逻辑器件实现对整个底层数据采集系统的逻辑控制，并给出了时序控制部分的仿真波形。
The system controls the logic of the data acquisition board by programmable logic device (PLD) with the center of the ARM microcontroller and FIFO memory and provides the simulate waveforms.
介绍了采用数字逻辑方法，用EPROM存储器为核心设计自动移印机。
This text introduces a method about designing an automatic pad-printing machine based on EPROM.
向存储器单元中加载可编程逻辑器件配置数据，来对可编程核心 逻辑进行配置以执行定制逻辑功能。
Programmable logic device configuration data is loaded into the memory elements to configure the programmable core logic to perform a custom logic function.
该存储系统完成了二维逻辑空间到物理空间上并行存储器模块的映射。
It maps a 2-d logic space onto physical parallel memory modules.
该存储系统完成了二维逻辑空间到物理空间上并行存储器模块的映射。
It maps a 2-d logic space onto physical parallel memory modules.
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