在电信号测量领域，逻辑信号的测量十分重要。
Logic signal measuring is very important in the field of electric signal measurement.
逻辑信号从高电平到低电平的转换被称为下降沿。
A transition in a logic signal from a logic high to a logic low is referred to as a falling edge.
逻辑信号按照预先设计的触发条件在特定时间段内采集。
The signals is sampled in the typical time segment according to the specified triggering condition.
标准并不试图将逻辑信号与任何特定种类的仪器信号相关联。
The Standard does not attempt to relate the logic signal to an instrument signal of any specific kind.
为解决数字电路插板的测试问题，设计了80路逻辑信号发生器。
To settle the problem of testing logic card, we have designed an 80 channels logic generator.
高电压电平漂移电路允许低压逻辑信号来驱动的IGBT在高达1200V一种操作高侧配置。
High voltage level-shift circuitry allows low voltage logic signals to drive IGBTs in a high side configuration operating up to 1200V.
该设计具体是，在EEPROM电路芯片加电时，通过一读出逻辑的自产生电路，产生一读出逻辑信号；
The design is characterized in that when the chip of an EEPROM circuit is powered on, a read-out logic signal is generated through a self-generating circuit of a read-out logic;
其特征是不要外接偏置电压源，而由一个特殊隔离变换器将输入逻辑信号变换为能快速开通或关断IGBT模块的驱动电力。
Its feature is that the input logical signal is converted to drive power by a special isolated converter, which makes a IGBT module turn on or off quickly, without any other biased voltage sources.
分析了各部分的电路结构及特点，讨论了PW M脉宽调制信号生成、逻辑信号综合、驱动控制及电流截止负反馈的具体应用，在此基础上给出了实验数据及结果分析。
It analyses some main circuits's features, including PWM signals, logic synthesis, driver and negative feedback of current cut-off and at last gives the result of experiment.
我们将项目按照功能中的逻辑关系划分为十二个组件，并使用OD C信号模板编辑ODC计划文档。
We divide our project into twelve components based on logical relationships among functions. We use the ODC signature template (Lotus 123) to make up our ODC planning document.
由于Python绑定模拟了逻辑接口，所以不可能不通过一个服务来发送信号。
Because the Python bindings model the logical interface, it is not possible to send a signal without it coming from a service. So this example also creates a service.
这种策略要求您了解基本操作系统内核提供的机制，并在程序逻辑中利用这些机制设计信号量使用方法。
This tactic requires that you review what the base OS kernel provides or advises in terms of designing the use of semaphores within your program logic.
应用该理论设计的对称三值电流型CMOS电路不仅具有简单的电路结构和正确的逻辑功能，而且能处理具有双向特性的信号。
The symmetric ternary current-mode CMOS circuits designed by using this theory not only have simpler circuit structures and correct logic functions, but also can process two-way signal.
作为另一个示例，选择信号的逻辑状态可响应于提供给脉冲频率检测器的电源电压的变化而改变。
As another example, the logic state of the select signal can be changed in response to a change in the power supply voltage provided to the phase frequency detector.
该仪器以最新的片上系统芯片FPSLIC为核心处理器，以RTX51为嵌入式操作系统，采用大屏幕液晶显示，实现了多路高速数字信号的逻辑分析。
This instrument uses System on Chip FPSLIC as its core processor, RTX51 as embedded systems and large LCD as displaying, which can analyse many channels logic signals.
分析了每一种信号的特征，提出并设计了逻辑芯片重构设计中信号类型识别算法。
This paper analyzes each kind of signal characteristics, proposes the signal type recognition algorithm in the logic chip restructuring design.
该自动化系统分为信号监测、PLC(可编程逻辑控制器)控制、上位机控制三大部分。
The system is composed of three subsystems, they are the signal monitor subsystem, the PLC (the Programmable Logical Controller) one and the host computer control ore.
例如，当涉及到数字逻辑时，由于即使瞬间中断信号，器件的状态也可能会发生变化，所以通常就需要采用热交换。
For ex ample, hot switching is typically used where digital logic is involved, because devices may change state if the power is interrupted even for a brief instant.
选择信号的逻辑状态可以例如响应于集成电路的温度变化而改变。
The logic state of the select signal can be changed, for example, in response to a change in the temperature of the integrated circuit.
该方案利用信号自身的特性，采用数字逻辑设计，有效避免了性能不高的锁相环的使用。
In the new scheme proposed, the phase lock loop is avoided and the digital logical circuit is used.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
采用干涉的能束控制，信号处理，放大和计算机逻辑。
Energy beam control, signal processing, amplification, and computer logic using interference.
介绍了一种大规模复杂可编程逻辑器件(CPLD)在雷达信号处理系统中动目标检测电路的应用及具体实现方法。
This paper introduces the application and design methods of a large scale Complex Programable Logic Device (CPLD) in radar signal processing system moving target detection circuit.
序流程图，在分析、处理随机信号逻辑关系的基础上，提出了PLC的编程方法。
After analyzing and processing the logical relationship of stochastic signal, the way of PLC program is put forward.
通过二、三值逻辑开关函数间的转换，系统地描述了三相CSR三值逻辑PWM信号发生中的状态切换；
A systematic description of the state switching in trilogic PWM signal generation of three-phase CSR by using the conversion between bilogic and trilogic switching functions.
通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。
By producing evaluating completion signal early and using DSDCVS logic to design computation circuit of reconfigurable cell, a modified control circuit is proposed.
阐述了信号光与串扰光的物理相干性与信号数字逻辑相关性问题。
The problem of physical coherence and digital logical correlation is stated in detail.
一个设计粗劣的电源网格很容易引起额外的逻辑延迟，信号完整性问题，甚至芯片的功能性错误。
A poorly designed power grid may easily lead to extra logic delays, signal integrity problems and even functional failures.
其第三个逻辑值(中间逻辑值)用作故障指示信号，或在脱机测试时应用。
The third logic value (the middle value) can be used as a fault indicating signal, or in off-line testing.
其第三个逻辑值(中间逻辑值)用作故障指示信号，或在脱机测试时应用。
The third logic value (the middle value) can be used as a fault indicating signal, or in off-line testing.
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