该方案将被叠加的字符或图像数据保存在FPGA内部的ROM中，由内部逻辑控制电路产生点阵时序，控制视频通道切换开关，完成叠加功能。
The data of overlapped characters and pictures are stored in the ROM of FPGA, The Times are generated by FPGA inner logic circuit to control the switch of TV channels to finish the overlapping work.
为使通道电阻引起的测量误差最小化，则采用4线切换电路。
To minimize measurement error due to channel resistance, use a four-wire switching circuit.
各通道设有通道信号切换开关，话筒输入设置高性能放大电路。
Each channel has a channel signal switch, high-performance microphone input amplifier circuit.
各通道设有通道信号切换开关，话筒输入设置高性能放大电路。
Each channel has a channel signal switch, high-performance microphone input amplifier circuit.
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