提出一款基于大规模可编程逻辑器件设计的具有多种功能的电力电子设备通用脉冲发生专用集成电路(ASIC)。
This paper presents a general pulse generator application specific integrated circuit (ASIC) for power electronics devices designed with the large-scale programmable logic devices.
介绍用通用阵列逻辑器件GAL设计十进制可逆计数器的方法。
The method of design of ten's carry reversible counter by use of common array logic element GAL is introduced.
介绍一种基于复杂可编程逻辑器件(CPLD)的通用高性能脉冲幅度分析(PHA)模块设计。
Based on a complicated programmable logical device (CPLD), a miniaturized universal pulse height analysis (PHA) module of high performance is realized.
提出了一种以复杂可编程逻辑器件（CPLD）和锁相环技术为核心的新型通用数字触发器，对其硬件电路和软件设计进行了详细分析。
To aim at the defect of the simulate trigger and the digital trigger with microcomputer, a new universal digital trigger based on CPLD and PLL is introduced.
结论采用复杂可编程逻辑器件替代通用数字集成器件，可提高系统的高频率特性，并提高信号源的信噪比。
So, complex programmable logic device can improve the system's high-frequency performance and signal to noise ratio.
结论采用复杂可编程逻辑器件替代通用数字集成器件，可提高系统的高频率特性，并提高信号源的信噪比。
So, complex programmable logic device can improve the system's high-frequency performance and signal to noise ratio.
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