并与功耗、面积约束一起，归纳出超前进位加法器的优化设计规则。
The optimal design rule of CLA was inducted from power dissipation and area constraint, reflect.
结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。
It shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.
该加法器适用于复合型加法运算，优于脉动进位加法器和超前进位加法器。
The prefix tree adder is useful in compound adder implementation. It is preferred over the ripple carry adder and the carry lookahead adder.
在本文中，我们提出8种不同的全加器电路，分别皆使用4位元链波进位加法器将其实现。
We proposed 8 kinds of full adder and all of them are realized in 4 bit ripple carry adder.
在一位数加多位数不进位加法口算中，口算时间差异主要源于运算时间差异和整合时间差异；
In the non-carry mental addition of 1-digit number and multi-digit number, mental arithmetic time differences lie in arithmetic time differences and integration time differences.
设计了4位QSERL串行进位加法器(RCA)电路，和相应的CMOS电路进行了功耗比较。
QSERL 4 bit carry ripple adder (RCA) is designed and compared with static CMOS counterpart.
采用一种新颖的实现方法，利用4 - 2压缩器和超前进位加法器来代替传统的加法，提高了运算速度。
This paper proposes a new method, which USES the 4-2 compressor and CLA instead of the traditional adder to improve the transformation speed.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
之后，是两个加法指令，第一个是普通相加，第二个是带进位相加。
Then comes two add instructions. The first is a normal add and the second one is add with carry.
提出了一种改进进位运算的32位稀疏树加法器。
A 32-bit sparse tree adder with modified carry tree structure is proposed.
首先介绍了常用并行加法器的设计方法，并在此基础上采用带进位强度的跳跃进位算法，通过逻辑综合和布局布线设计出了一个加法器。
On the basis we design an adder by the adoption of carry skip algorithm with carry strength signals and implement, through logic synthesis and layout.
优化方块分配的进位跳跃加法器可以缩短关键路径的延时。
The carry skip adder optimal block sizes can minimize critical path delay.
提出了一种新的获得二级进位跳跃加法器优化方块分配的算法。
A new type of optimal block distribution algorithm of two level carry-skip adder was described to determine optimal block distribution sizes.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
Addend and BeiJiaShu as input, and the device for output with binary for half a gal device.
加法器是产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。
Addend and the summand input, and digital and carry the output device is a half adder.
提出了一种基于方块超前进位的快速进位跳跃加法器。
A fast carry-skip adder is proposed based on variable-sized two-level block carry-lookahead logic.
提出了一种基于方块超前进位的快速进位跳跃加法器。
A fast carry-skip adder is proposed based on variable-sized two-level block carry-lookahead logic.
应用推荐