缓冲存储器周期的一部分，在这期间，逻辑与算术运算器必须中止操作或不能与存储器传输信息。
A portion of the buffer cycle in which the logic or arithmetic unit must cease operation or neither will be able to communicate with the memory unit.
执行过程中的一个阶段所需的时间，在此期间，计算机从主存储器中取出指令或操作数，并将其存入控制器或运算器的寄存器中。
The part of execution in which an operand or instruction is read from main storage and written into a control unit or arithmetic unit register.
并行计算机是一种具有多个运算器，能作并行操作或并行处理的计算机。
Parallel computer is a computer with multiple logic or arithmetic units enabling it to perform parallel operations or parallel processing.
并行计算机是一种具有多个运算器，能作并行操作或并行处理的计算机。
Parallel computer is a computer with multiple logic or arithmetic units enabling it to perform parallel operations or parallel processing.
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