即“矩阵实验室”，它是以矩阵为基本运算单元。
MATLAB, "Matrix lab, " It was based on the matrix of the basic computing unit.
提出了一种可综合算术运算单元的性能评估与建模方法。
A performance evaluation and modeling method for synthesizable arithmetic circuit is proposed.
运用流水线技术对单精度浮点乘法和加法运算单元进行了优化设计。
For optimizing floating-point units, a design based on pipeline techniques is described in this paper.
采用改进的蝶形运算单元，减小了系统的硬件消耗，改善了系统的性能。
Because of the utilization of improved butterfly processor, hard-ware consumption is reduced and the performance is improved.
设计方案采用了单个蝶型运算单元以达到控制FFT处理器规模的目的。
Furthermore, single butterfly processing element is employed to control FFT processor scale.
紧接着讨论了LDPC译码器中的核心运算单元一校验功能单元的硬件设计。
Then it mainly discusses the hardware design of the key unit in LDPC decoder-check functional unit.
算法的硬件结构由模乘控制器、模幂控制器、数据寄存器和模乘运算单元构成。
The hardware architecture is made up of modular controller, modular exponentiation controller, data register, and modular multiplication operation units.
实验结果表明，该有限域模乘指令和硬件运算单元具有较高的执行效率和较好的灵活性。
Experimental results show that, the modular multiplication instruction and hardware unit presented in this paper can achieve high performance and guarantee high flexibility.
论述了一种结构精简且高效的浮点数蝶形运算单元设计，单元内部模块的使用效率接 近100%。
This paper presents an efficient design of butterfly unit with simplified structure. The occupating coefficient of inner modules of the unit is almost 100%.
算术逻辑运算单元（ALU）决定着中央处理器（CPU）的性能，而加法器又决定着ALU的性能。
The arithmetic logic unit(ALU) decides the performance of the Central Processing Unit(CPU), while the adder decides that of the ALU.
采用直接和随机测试方法，对浮点运算单元进行了测试和验证，代码覆盖率和功能覆盖率都达到了100%。
Tests and verifies the floating point unit in direct and random methods, with 100% functional coverage and code coverage.
文章给出了一种RSA密钥生成的VLSI实现方案，在RS A协处理器基础上增加若干运算单元，来完成RSA密钥生成和加解密操作。
A new approach to VLSI implementation of RSA key generation is proposed in the paper, in which logic units are added to the RSA cryptography coprocessor to realize RSA key generation and encryption.
处理器将数据流解释为要执行的指令，它拥有一个或多个处理单元，用于执行整数和浮点运算以及更高级的计算。
A processor interprets a stream of data as instructions to execute; it has one or more processing units that perform integer and floating-point arithmetic as well as more advanced computations.
这一单元确定要执行这些运算中的哪一个。
做为基本计算单元之线性方程组，以矩阵形式表示线性方程组，基础矩阵运算。
Linear equation sets as basic computational unit, expressing linear equation sets in matrix form, basic matrix operations.
这种方法的主要优点是运算简单，节省内存单元，从而可以提高话音识别的速度和精度。
The main advantages of this method is operation simple and save memory, so that it may have higher speed and accuracy for speech recognition.
利用DSP高速运算性能以及内部控制单元简化了系统的软硬件，实现了步进电机的高精度细分驱动。
Using DSPs high speed operation performance and its inner control unit, simplified the systems software and hardware, achieved stepper motors high precision subdivision drive.
算术逻辑单元，用来进行算术逻辑运算。
The arithmetic logic unit (ALU), which performs arithmetic and logical operations.
通过有效利用图形硬件的图形处理单元(GPU)的运算能力和可编程性，将大量计算从CPU分离出来。
With the efficient use of computation capacity and programmability provided by graphics processing unit (GPU) of underlying graphics hardware, most of computation from CPU are isolated.
计算机中，解释并执行指令的一种功能单元。注：处理器至少包含有一个指令控制器和一个算术与逻辑运算器。
In a computer, a functional unit that interprets and executes instructions. Note: a processor consists of at least an instruction control unit and an arithmetic and logic unit.
文中绐出了两种基于特殊蝶形运算的处理单元和两种计算DCT，DHT（DWT）和DFT的脉动阵列实现。
In this paper, we preset the processing elements based on a special butterfly computation and discrible the systolic array implementations for computing DCT, DHT(DWT) and DFT respectively.
本文提供一种新型摸拟运算控制多电机同步系统，它由模拟调速率系统组成各单元浮动，然后组合成多电机同步系统。
Develops a new-type analog calculation control multi-motor synchronous system composed of analog-regulating speed systems each making up a unit drirve.
这类单元与其他类型的杂交模型相比，精度高且能较好地避免矩阵求逆运算，具有较好的实用性。
Matrix inversion can be avoided, in comparison with conventional hybrid element, the method is more convenient in practical application.
在各单元中包括寄存器，各寄存器与时钟脉冲同步，依次取得逻辑运算结果并加以保存。
Each cell contains a register. Each register successively acquires logic calculation results in synchronization with a clock and maintains them.
运算器：运算器是数据加工处理部件，它是由算术逻辑单元(alu)、累加器、数据缓冲器等组成。
Arithmetic unit: arithmetic unit is a data processing unit that consists of arithmetic logic unit (ALU), accumulator, data buffer, ect.
把全部有效实体单元进行3维实体布尔运算，得到牙齿的实体模型。
All obtained valid 3d solid elements are combined with Boolean operation, and the volumetric model of a tooth is then achieved at last.
把全部有效实体单元进行3维实体布尔运算，得到牙齿的实体模型。
All obtained valid 3d solid elements are combined with Boolean operation, and the volumetric model of a tooth is then achieved at last.
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