主控器设计是边界扫描测试系统设计的重点。
The design of a BSM is the key problem of the implementation of the Boundary Scanning Test System implementation.
逻辑簇的边界扫描测试存在一些不可忽视的重要问题。
Some problems in logic cluster boundary scan test could not be neglected.
系统级可测性设计主要是将存储器BIST与ARM核的边界扫描测试相结合。
SRAM BIST is also combined with ARM core's boundary scan testing during system level DFT.
本文详细介绍了边界扫描测试的原理、结构，讨论了边界扫描测试技术的应用。
The working principle and architecture of BST is introduced in this paper and its applications are discussed.
本文概要论及与测试相关的设计特性，详细讨论了不同MCM的边界扫描测试策略。
This paper Outlines the design of features related to test and then details the Boundary Scan test strategies developed for different MCM.
采用DSP和边界扫描总线控制芯片74lvt8980设计边界扫描测试控制器。
A boundary scan controller with the USB interface is designed. DSP and 74lvt8980 are adopted to control the boundary scan bus.
研究了目前较常用的边界扫描测试技术的原理、结构，并给出了边界扫描技术的应用。
In this paper, the theory and architecture of boundary scan test technology is introduced and researched, then its application is given.
目前常见的可测试性设计方法主要有改善设计法、结构设计法和边界扫描测试法等几种。
There are some common methods of design for testability, such as boundary scan test and so on.
介绍了数据采集的原理和ASIC的基本功能、实现以及JTAG的边界扫描测试技术。
In this paper, the principle of data collection, the basic function and implementation of asic and the technology of JTAG BST are presented.
本文介绍了开发的边界扫描测试仪样机的工作原理，并着重论述了其软件开发的几个重要问题。
In this paper, a boundary-scan prototype tester is introduced. Some problems in developing its software system are emphasized.
本文在阐述边界扫描测试原理的基础上，重点讨论了所开发的一种用于边界扫描测试的虚拟仪器。
With the analysis of the boundary scanning principle, this paper discusses a virtual instrument for boundary scanning test.
本文还讨论了两种智能故障诊断技术，即专家系统智能故障诊断技术和边界扫描测试智能故障诊断技术。
The paper also discusses two intelligent fault diagnostic methods: expert system intelligent fault diagnostic method and boundary-scan technique intelligent fault diagnostic method.
随着芯片集成度和印刷电路板复杂度的不断提高，边界扫描测试技术在芯片故障检测中的应用越来越广泛。
With the continual improvement of the chip's integration level and complexity of print circuit board, the application of boundary scan test technology becomes wider and wider in testing ICs.
分别给出了边界扫描测试和分频器测试两种测试方案，并对两种方案进行了比较，指出了各自的适用范围。
Two test methods, both test on boundary scan and test-by-divider, are described in details, especially focusing on the maximum output frequency, the range of output frequency and the time to lock.
本文论述了板级边界扫描测试存取口的故障模型和测试原理，并针对全边界扫描印制板提出了一种故障覆盖率高、测试时间短的测试算法。
This paper describes the fault models and test principles of the BS test access port (TAP) lines on PCBs. A test algorithm with high fault coverage and short time is then presented fort…
JTAG边界扫描机制是用于在线导通测试的新技术，利用JTAG可以在数分钟内查出复杂插件和系统的全部导通故障。
JTAG Boundary Scan is a new technique for connection test. With the help of JTAG, we can find out all connection faults of a complicated board or system.
在某计算机系统中设计了基于JTAG边界扫描计算机插件或系统在线导通测试系统，这是一个新颖通用的系统。
We have developed a new On-line Connecting Test System based on JTAG boundary scan for computer plug-unit or system.
IEEE1149标准及其子标准是基于边界扫描的测试技术，它们针对不同的应用环境采用相应的技术标准。
IEEE1149 standard and its. X sub standards are based on boundary scan technique, different standards can be appropriately selected for various of applications.
该文在研究边界扫描体系结构和TAP接口控制器的基础上，在一个测试系统中，实现了基于JTAG规范的主ta P接口设计。
On the basis of research on the bound ary-scan architecture and TAP controller, the paper implements a design for a t ap interface based on JTAG specification in a test system.
本文在对目前主要的可测性设计方法进行研究的基础上，根据所设计CPU的结构特点，采用了边界扫描技术和基于BILBO的内建自测试技术结合的可测性设计方案。
Based on the research of primary DFT method and the structure characteristic of designed CPU, the article combines the boundary scan and Build-In Self-Test based on BILBO to test.
边界扫描技术是一种标准的数字电路测试及可测试性设计方法，它在工业界得到了广泛的应用。
As a standard technique of test and Design-For-Testability for testing the digital printed circuit board, Boundary-Scan technique has obtained widespread application in electronic equipment.
电子产品微型化使自动测试成为必然，而边界扫描技术则使自动测试成为可能。
The miniaturization of electronic products results in automatic testing, which is made possible by boundary scan technology.
扫描技术和边界扫描技术是目前可测试性设计的主流技术，可分别用来解决芯片内部与芯片之间的可测试性问题。
Scan technique and boundary scan technique are the main stream technology of current DFT technique. They can solve the internal testable problems and the connection problems between ICs respectively.
文中介绍JTAG边界扫描的概念、技术特点，以及在芯片功能测试、系统诊断、仿真、性能分析和导通测试方面的应用。
This paper focuses on the JTAG ideas and technical characteristics and summarizes the JTAG usage in chip function test, system diagnosis, simulation, performance analysis and conduction test.
边界扫描技术与功能测试的结合，可以扩展边界扫描技术的应用范围，实现了更高的测试覆盖率。
Combining boundary scan with functional test, expanded application of boundary scan and larger testing coverage may be realized.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
该电路可实现测试、编程功能，并符合IEEE1149.1边界扫描标准的规定，测试结果达到设计要求。
Test results show that the FPGA chip can realize the desired functions of test and programming in accordance with IEEE1149.1 boundary scan standard, and meets the requirement of the design.
基于IEEE 1149.1标准的边界扫描技术(BST)作为一种标准化的可测性设计方法，弥补了传统测试的缺陷，为复杂的电路互连提供了测试手段。
As a standard DFT method, IEEE 1149.1 boundary-scan technique (BST) provides measures to complex interconnect test and can well make up the shortcoming of traditional test techniques.
在对描述器件边界扫描特性的BSDL语言进行了深入研究之后，将其应用于边界扫描自动测试图形生成atpg与故障诊断软件中。
The BSDL language that describes boundary scan components is thoroughly studied, and then applied to boundary scan ATPG tools and fault diagnosis software.
本文提出将测试领域成熟的边界扫描技术应用在实验系统中，解决配置和验证两大关键问题。
The paper proposes applying boundary-scan technology which is widely used in the domain of test to the computer hardware experiment to resolve the two crucial problems of configuration and test.
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