关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
延迟电路可通用于输出时钟的频率调整以及相位调整这两方面。
The delay circuit is used for both frequency and phase adjustments of the output clock.
论文中还给出了开关量输入、开关量输出、通信模块、时钟电路、数据存储器、按键电路和频率跟踪电路等各功能模块的选择方法和设计原理。
And the selection and design of switch-in module, switch-out module, communication module, clock module, data storage module, keys module and frequency detecting module are also discussed.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
AD7764的采样速率、滤波器转折频率和输出字速率由外部时钟频率决定。
The external clock frequency applied to the AD7764 determines the sample rate, filter corner frequencies, and output word rate.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
当器件的时钟频率，数据是转向了串行输出齐晖。
When the devices are clocked, data is shifted toward the serial output QH.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
采样速率、滤波器转折频率和输出字速率由ad7760的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
采样速率、滤波器转折频率和输出字速率由ad7762的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762.
像素时钟输出频率范围从10mhz到140mhz的采样250ps的峰峰值抖动。
Pixel clock output frequencies range from 10mhz to 140mhz with sampling clock jitter of 250ps peak to peak.
频率比较器比较基准时钟和输出时钟的频率，并输出频率比较信号。
A frequency comparator compares the frequency of a reference clock with that of an output clock and outputs a frequency comparison signal.
相位频率检测器比较基准时钟信号和反馈时钟信号从而在一个或更多个输出信号中生成脉冲。
A phase frequency detector compares a reference clock signal to a feedback clock signal to generate pulses in one or more output signals.
假设高信号使能，计数器每个时钟周期进行计数，PWM输出的频率为时钟频率的2次幂分频。
Suppose that Enable is high, the counter counts up every clock cycle, and the frequency of the PWM output is the clock frequency divided by 2 count bits.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
由于采样速率、滤波器转折频率、建立时间、群延迟和输出字速率与外部时钟频率呈比例变化关系，因此这些参数也会相应降低。
The sample rate, filter corner frequency, settling time, group delay and output word rate will be reduced also, as these are proportional to the external clock frequency.
应用推荐