这样，这里的%eax既可以用作输入寄存器，又可以用作输出寄存器。
输出数据通过串行或并行端口从输出寄存器中存取，这可实现与现代微控制器和数字信号处理器的轻松、高速接口。
The output data is accessed from the output register through a serial or parallel port. This offers easy, high speed interfacing to modern microcontrollers and digital signal processors.
我们的示例显示了GCC如何分配寄存器，以及它如何更新输出变量的值。
Our example shows how GCC allocates registers, and how it updates the value of output variables.
这个示例程序还输出了当时通用寄存器的值。
The sample program has also dumped the general purpose register values in this case.
下面的输出显示了kprobe 的地址以及 eflags寄存器的内容
The following output shows kprobe's address, and the contents of the eflags registers
在下面的示例中，cpuid指令采用%eax寄存器中的输入，然后在四个寄存器中给出输出：% eax、%ebx、%ecx、%edx。
In the following example, the cpuid instruction takes the input in the % eax register and gives output in four registers: % eax, % ebx, % ecx, % edx.
将磁心存储器读出放大器的输出选通到寄存器的触发器中的一种脉冲。
A pulse to gate the output of a core memory sense amplifier into a trigger in a register.
当主控门打开时，经过转换的输入信号脉冲通过它进入计数寄存器，并在此统计，然后通过显示电路输出。
While the main gate is open, the conditioned input signal pulses are passed through to the counting register, where they are tallied and then scaled for output by the display circuitry.
按照逻辑芯片设计特点，将芯片工作时的信号分为4种：时钟信号、输入信号、组合输出信号和寄存器输出信号。
According to the logic chip design feature, the chip work's time signal can be divided into 4 kinds: clock signal, input signal, combination output signal and register output signal.
每个器件都有一个八位CMOS移位寄存器和CMOS控制电路，八个CMOS数据锁存，八个双极电流吸收达林顿输出驱动器。
Each device has an eight-bit CMOS shift register and CMOS control circuitry, eight CMOS data latches, and eight bipolar current-sinking Darlington output drivers.
之后，驾驶员命令设备来完成其工作(通过操纵其寄存器)和直接在设备传送输出数据在存储器中分配的缓冲区。
Then the driver commands the device to do its job (by manipulating its registers) and the device transfers output data directly to the allocated buffer in the memory.
研究了串行输入，并行输出单向移位寄存器的功能。
The function of the single-direction shift register which is serial input and parallel output is mainly studied.
例如，寄存器可包括用在8 - PS K模式下的斜坡输出值。
For example, the register may include ramp output values for use in an 8-psk mode.
在这些替代实施例中，在所述一个逻辑模块中寄存器的数量超过组合输出信号的数量。
In these alternative embodiments, the number of registers exceeds the number of combinational output signals in the one logic module.
一种集成电路，包括多个逻辑元件(LE)和一个部分扫描寄存器，每个逻辑元件具有多个输出。
An integrated circuit is described as comprising a plurality of logic elements (LEs), each of which having a plurality of outputs, and a partial scan register.
利用一个片内控制寄存器，用户可以设置不同的工作条件，包括模拟输入范围和配置、输出编码、功耗管理及通道序列化。
An on-chip control register allows the user to set up different operating conditions, including analog input range and configuration, output coding, power management, and channel sequencing.
采样速率、滤波器转折频率和输出字速率由AD7763的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7763.
基于EPP协议的特点，应用复杂可编程逻辑器件(CPLD)开发了移位寄存器输出接口。
Based on the properties of Enhanced Parallel Port (EPP), an interface of shift register output has been developed using Complex Programmable Logic Device (CPLD).
采样速率、滤波器转折频率和输出字速率由ad7760的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies, and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7760.
采样速率、滤波器转折频率和输出字速率由ad7762的外部时钟频率与配置寄存器共同设置。
The sample rate, filter corner frequencies and output word rate are set by a combination of the external clock frequency and the configuration registers of the AD7762.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
在串行CRC编码实现中，移位寄存器主要完成将并行输人数据转换成串行输出数据的功能，是整个设计的重要组成部分。
The shift register's function is completion of parallel data input into serial data output. The design of shift register is an important part in the realization of CRC code.
到输出的时候，只需直接追踪到正确的最初寄存器加以输出，以上过程省去了每段的回溯过程，可省去判断位元的存取和存储器模块。
When being output, the correct initial register is traced and output. The process saves the back-track process of each block, and the judging process of the access and the memory module of the bit.
到输出的时候，只需直接追踪到正确的最初寄存器加以输出，以上过程省去了每段的回溯过程，可省去判断位元的存取和存储器模块。
When being output, the correct initial register is traced and output. The process saves the back-track process of each block, and the judging process of the access and the memory module of the bit.
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