建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
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