最后，通过对误码性能和系统联合锁定时间进行仿真，验证了数字解调器性能，并在FPGA中实现了载波恢复模块。
Finally, the performances of this digital demodulator are tested through the simulation of BER and the system joint lock-time, and a carrier recovery module is implemented in FPGA.
最后，通过对误码性能和系统联合锁定时间进行仿真，验证了数字解调器性能，并在FPGA中实现了载波恢复模块。
Finally, the performances of this digital demodulator are tested through the simulation of BER and the system joint lock-time, and a carrier recovery module is implemented in FPGA.
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