实验结果表明，该译码器具有时序控制简单、译码时延小和资源利用率高的特点。
The experimental results show that the decoder possesses simple logic control, low time delay and high resource using.
串并联混合的加比选单元，可以降低PLVA译码的资源占用及译码时延，提高译码速率。
The series-parallel hybrid add-compare-select units can reduce the resource occupation and decoding delay of the PLVA decoding, and improve the decoding speed.
与采用传统回溯法的译码器相比，该译码器具有较低的译码时延、有效的存储空间管理和较低的硬件复杂度。
This Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoders using traditional trace-back methods.
经仿真验证，该准则在译码性能几乎没有下降的同时，有效的减少了平均迭代次数，降低了时延。
The corresponding simulation and analysis shows that the new criterion does help reduce the average number of decoding iteration and the time delay while the BER performance is almost not degraded.
经仿真验证，该准则在译码性能几乎没有下降的同时，有效的减少了平均迭代次数，降低了时延。
The corresponding simulation and analysis shows that the new criterion does help reduce the average number of decoding iteration and the time delay while the BER performance is almost not degraded.
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