针对这个问题给出位线“间隔译码”的组织结构，有效地降低了存储器读写时寄生rc所带来的串扰。
In this paper, we discuss a new memory array-interval decoding architecture, which decreases cross talk parasitical rc aroused effectively during the period of read and writing operation.
控制部件从存储器中取出指令，并确定其类型或对之进行译码，然后将每条指令分解成一系列简单的、很小的步骤或动作。
The control unit fetches instructions from memory and determines their type or decodes them. It then breaks each instruction into a series of simple small steps or actions.
在此提出了一种幸存路径存储器的新实现方法，与传统的回溯法和寄存器法相比，该方法具有存储器用量少、译码延迟小的特点。
Compared to traditional register-exchange and trace-back methods, the main advantages of this method lie in less memory and little decoding delay.
控制单元由程序存储器ROM、指令译码器、地址生成模块、程序计算器PC 组成。
The control path contain Instructor ROM, instructor register, instructor decode unit, address creating module and Program Counter (PC)module.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
存储器采用六管CMOS存储单元、锁存器型敏感放大器和高速译码电路，以期达到最快的存取时间。
A fast access time is achieved by using six-transistor CMOS memory cell, latched sense amplifier, and high-speed decoder circuit.
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