集成电路(VLSI)设计流程中，设计规则检查(DRC)是关键一环。
In VLSI design flow, design rule checking (DRC) is an important step.
本文给出了一种基于设计规则检查之上的一维版图压缩算法——局部的动态的一维压缩算法rdoc。
Regional Dynamic One-Dimensional Compaction Algorithm (RDOC) based on design rule check is given in this paper, which is very suitable for physical layout.
然后也检查了我们是否打破了我们在项目中所使用平台的设计规则。
The latter were asked to check that we did not break any system design rules valid on the platform we were using for this project.
除此之外，数据登录表格能被设计自动地为错误检查而且避免特定类型的会违犯确定的规则数据登录。
In addition, data entry forms can be designed to automatically check for errors and prevent certain kinds of data entry that would violate established rules.
介绍了ASIC设计过程中测试矢量的产生与验证步骤，包括激励编写规则、波形检查、测试矢量的获得以及测试矢量的验证。
The test vectors generation and verification in ASIC design are introduced, including stimulus writing guidelines, waveform audit, vectors strobe and simulation used for test vectors.
定义印制电路板的布局规则，对于PCB的设计的进行检查的改进。
Define PCB layout rules and review work of PCB designers on an ongoing basis.
在完成版图设计后，还进行了几何规则 检查和版图与电路一致性的 检查。
Design flow of analog circuit begins with drawing schematic and includes simulation, layout, DRC/LVS check, parasitic extraction and post-simulation.
在完成版图设计后，还进行了几何规则 检查和版图与电路一致性的 检查。
Design flow of analog circuit begins with drawing schematic and includes simulation, layout, DRC/LVS check, parasitic extraction and post-simulation.
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