频率计由时间闸门电路和计数器组成。
本文介绍了一种同步测周期计数器的设计，并基于该计数器设计了一个高精度的数字频率计。
The design of a counter measuring synchronous period is introduced in this paper. And based on it, a high precision digital cymometer is designed.
计数式频率计的选通门一般与被测信号是不相关的。
The strobe signal is not commonly associated with the signal tested.
用CPLD作频率计数字电路的核心部件，可简化频率计的硬件电路，提高系统的工作速度，节约设计与制造成本。
Using CPLD as the core of the circuit, it can simplify the hardware circuit, improve operational speed and save production cost.
用CPLD作频率计数字电路的核心部件，可简化频率计的硬件电路，提高系统的工作速度，节约设计与制造成本。
Using CPLD as the core of the circuit, it can simplify the hardware circuit, improve operational speed and save production cost.
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