FFT是数字信号处理中的一种非常重要的算法，蝶形运算模块是FFT处理其中的重要构造模块。
FFT is a very important algorithm in digital signal processing, and butterfly operation modules are important construction modules in FFT processor.
文中绐出了两种基于特殊蝶形运算的处理单元和两种计算DCT，DHT（DWT）和DFT的脉动阵列实现。
In this paper, we preset the processing elements based on a special butterfly computation and discrible the systolic array implementations for computing DCT, DHT(DWT) and DFT respectively.
采用改进的蝶形运算单元，减小了系统的硬件消耗，改善了系统的性能。
Because of the utilization of improved butterfly processor, hard-ware consumption is reduced and the performance is improved.
实验证明，这种改进结构既保证了蝶形运算的速度，又节约了芯片资源，适合在FFT芯片设计中使用。
It is proved in the experiments that the improved architecture not only guarantees the velocity of FFT butterfly but also economizes the chip resources and ADAPTS to FFT chip design.
首先将二维idct转换为两个一维idct变换，根据蝶形算法进一步转换为矩阵的乘加运算。
First, the 2-d IDCT is transformed into two cascaded 1-d IDCT. Then 1-d IDCT can be implemented by multiplication and addition of matrix according to butterfly computation.
本文研究了基2的时域抽取快速傅立叶变换各阶段的并行性，并据此设计了相应的蝶形和倒序运算核，在GPU上实现了二维fft运算。
This paper studies the parallelism of the different stages of decimation in time radix 2 FFT algorithm, designs the butterfly and scramble kernels and implements 2d FFT on GPU.
给出了频域抽取二维向量基快速傅里叶变换算法，针对二维频域信号采用频域抽取方法，导出了该快速算法蝶形运算的一般形式并给出了算法实现流程图。
In accordance with the requirements of high speed digital signal processing, the algorithm of radix-4 implemented with FPGA and the integrated architecture and butterfly unit are analyzed.
论述了一种结构精简且高效的浮点数蝶形运算单元设计，单元内部模块的使用效率接 近100%。
This paper presents an efficient design of butterfly unit with simplified structure. The occupating coefficient of inner modules of the unit is almost 100%.
论述了一种结构精简且高效的浮点数蝶形运算单元设计，单元内部模块的使用效率接 近100%。
This paper presents an efficient design of butterfly unit with simplified structure. The occupating coefficient of inner modules of the unit is almost 100%.
应用推荐