VLSI集成电路芯片测试技术正在向高层次测试推进。
The VLSI testing is being pushed to the high-level based technology.
芯片测试结果的正确也验证了这种时钟树综合方案的有效性。
The correct test results of the chip also verify the effectiveness of this clock tree synthesis program.
文章提出了一种混合定变长码的测试数据压缩方案，该方案可以有效压缩芯片测试数据量。
A test data compression scheme based on fixed and variable length coding (FAVLC) is presented, by using which the test data can be compressed efficiently.
随着集成电路设计进入超深亚微米阶段，电路复杂度不断提高，芯片测试面临着巨大的挑战。
As the integrated circuit design has stepped into the deep ultra-submicron stage, the complexity of the circuit increases continually, chip test faces very huge challenge.
此次裁员是由于几家亚洲的芯片测试工厂的关闭及位于俄勒冈和加州的几个工厂停产造成的。
The cuts result from the closing of three chip-testing facilities in Asia and halting operations at plants in Oregon and California.
在芯片测试中，若引线焊盘上的铝层被探针扎穿，就会影响引线键合的牢固性和器件的可靠性。
If the Al film on the bond pad is pierced through by the probe in wafer probing, the wire bonding strength and device reliability would be affected.
通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
建立一个统一的芯片测试和芯片诊断调试接口，形成以边界扫描链为主体，全扫描链为补充的芯片测试机制。
Establishing an unite interface of chip test and debug which embodies the boundary scan and complements the full scan.
介绍了一种高速7位DAC的设计及芯片测试结果，该DAC选取高5位单位电流源，低2位二进制电流源的分段结构。
This paper describes the design and the test results of a 7-bit high-speed CMOS DAC, which is implemented using a segmented architecture with 5 MSBs in unary way and 2(LSBs) in binary way.
测试调度是系统芯片测试的一个重要方面，它用于确定把芯片上芯核的测试集分配给测试存取机制的方法，以使得总的测试时间最少。
Test scheduling determines an assignment of cores to test access mechanism such that the overall test application time of system on chip (SOC) is minimized.
本周早先时候，世界最大的芯片制造商intel表示由于产品需求巨大降低，公司会裁员至少5000人，并且关闭旗下的测试和生产厂。
Earlier this week, Intel, the world's largest chip maker, said it would lay off at least 5, 000 people and close some test and manufacturing plants to deal with vanishing demand for its products.
提供针对在嵌入式或运行时目标中执行的软件的运行时分析和组件测试功能——从8位微芯片到64位运行时操作系统。
Provides runtime analysis and component testing capabilities for software executing on embedded or real-time targets — from 8-bit microchips to 64-bit real-time operating systems.
其中一个问题是芯片太“过于智能”了——与普通芯片的数字脉冲输出不同，它的输出是模拟信号，因此用于数字芯片的测试程序被它干扰了。
Part of the problem is that the chip is just too intelligent - rather than a standard digital pulse it produces an analogue output that flummoxes the standard software used to test chips.
针对TSAT专用集成电路(ASIC)的测试，充分展示了微芯片在航空飞行中的功能、速度和匹配性。
Tests of the TSAT Application Specific Integrated Circuit (ASIC) demonstrated the microchip \ 's functionality, speed and suitability for spaceflight.
一枚叫做生物芯片的小型监测仪器通过镊子放入球员嘴里，芯片上涂有基因的变体，用以测试。
Swabs were taken from inside the players' mouths and the DNA placed on a small testing device called a biochip. This had been coated with the genetic mutations for which they were being tested.
测试结果表明，SAD芯片的实际工作性能良好，有效地解决了WPAN的实用性、高效性和可靠性问题。
The test results show that actual working performance of SAD chipset is good, and is achieves practicability, efficiency and dependability for WPAN.
另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
探针卡，该探针卡的设计方法，以及使用该探针卡测试半导体芯片的方法。
Probe card, method of designing the probe card, and method of testing semiconductor chips using the probe card.
验证测试担负着检测芯片设计和检验测试程序正确性的双重任务，是芯片开发中不可或缺的重要环节。
The validation test has been a necessary and important process, which assumes the double task in checking the correctness of both the design and test programs.
对芯片管脚的测试可以提供100%的故障覆盖率，且能实现高精度的故障定位。
For testing chip pins, the fault coverage can reach 100%, and the fault position can be positioned with high accuracy.
失效分析是验证测试的重要方面，它为探求芯片失效机理与优化验证测试流程奠定了基础。
Failure analysis is a main aspect of the validation test and it provides the fundamental ways for tracing the failure mechanisms and optimizing the validation test flow.
本文提出了一种基于指令系统的MB86901SPARCRISC芯片的行为功能级测试方法。
This paper describes an approach to instruction system-based on behavioral functional level test of MB86901 SPARC RISC chip.
本文就主流宽带PON技术、系统测试、芯片和设备进展进行简要介绍，最后对其应用予以展望。
This paper introduces the major broadband PON technologies, the test of PON system, and the progress of relevant chips and equipments, and finally gives an expectation of their applications.
可测试性设计是现代芯片设计中的关键环节，针对无线接入芯片的可测试性设计对测试技术有更高的要求。
Design for test is an important process in the chip design nowadays, testability design of wireless chip needs a much higher requirement of test technology.
本发明公开一种无线射频识别芯片的测试模块及其使用方法。
The invention discloses a testing module of wireless radio frequency recognition chip and an application method thereof.
这颗蓝牙射频调制解调芯片的实际测试数据也会被引用，以佐证和加深文章中的讨论。
Actual results from a Bluetooth radio modem chip will be used to further the discussion.
在阐述数字复解调原理的基础上实现了一个基于专用芯片的数字复解调测试系统。
By introducing the principle of digital IQ demodulation, we realizes a digital IQ demodulation system with the special large scale integration chip.
在阐述数字复解调原理的基础上实现了一个基于专用芯片的数字复解调测试系统。
By introducing the principle of digital IQ demodulation, we realizes a digital IQ demodulation system with the special large scale integration chip.
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