本论文研究的前期任务是，以德州仪器TMS320C25数字信号处理器为目标，研制指令与时序完全与之兼容的数字信号处理器芯片核NDSP25。
The first mission of the dissertation is to design NDSP25 processor, which is fully compatible with the TI TMS320C25 DSP processor in instruction set and cycle timing.
“现在已经有了8核芯片，关系型数据库能够真正利用这些优势，”Leffler说。
"Now you have eight-core chips, and relational databases can really take advantage of that," says Leffler.
POWER6芯片和PowerVM 的一般功能支持每个核10 个分区，最大限制是每台服务器 254 个分区。
With the POWER6 chip and PowerVM’s general capabilities of allowing for 10 partitions per core, the maximum limit was 254 partitions per server.
与之相反的是，近年来出现的通过将多个处理引擎或者“核”封装在一个芯片上的现象，又展现了另一种魅力。
Instead, extra oomph has been added in recent years by packaging multiple processing engines, or "cores", inside a single chip.
英特尔公司作为全球最大的芯片制造商，向世人展示了48核处理器，并且在几年内还将推出数百核处理器。
Intel, the world's biggest chipmaker, has demonstrated a 48-core processor, and chips with hundreds of cores seem likely within a few years.
对于现今个人计算机中的多核芯片（也许四核或六核甚至八核）来说，分解计算任务并不是个大问题。
With the multicore chips in today’s personal computers, which might have four or six or even eight cores, splitting computational tasks hasn’t proved a huge problem.
a 5是双核芯片，据说可以为iPad带来成倍的处理速度和9倍的视频效果。
The A5 is a dual core chip and said to bring up to double the processing speed and 9 times video performance.
Power 780的主要特性之一是TurboCore技术，这种技术允许用更少的核运行系统，从而利用芯片上的其他核增加缓存。
One major feature of the Power 780 is TurboCore technology, which gives you the option to run the system with fewer cores to take advantage of increased cache from other cores on the chip.
这样一来，研究人员在现场可编程门阵列芯片上创造出来1000个迷你电路，成功地将电脑芯片变成1000核处理器，每个核心在各自的指令下执行任务。
By creating more than 1,000 mini-circuits within the FPGA chip, the scientists effectively turned the chip into a 1,000-core processor - each core working on its own instructions.
苹果公司的电脑机型全部使用英特尔的双核处理器，除去那些价格最高昂的台式机之外，它们配备的是四核芯片。
Apple models all use Intel's dual-core processors, except for the highest-priced desktops, which come with quad-core chips.
这些手机都将采用Android 2.2系统或是其2.3升级版，配有4.3英寸显示屏以及双核处理器（摩托罗拉的DroidBionic甚至还配有NVIDITegra2的芯片）。
These devices all run Android 2.2, with likely upgrade or launch with Android 2.3, have 4.3 inch displays, and dual-core processors (the Droid Bionic even has the NVIDI Tegra 2 chip).
另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
并对PCI总线在氡室检测系统中的具体硬件系统结构、控制芯片与驱动软件设计，与PCI总线对核谱转换的传输性能作了阐述。
And the specific hardware system structure, control slug and the design of drive software and the transmission performance of PCI bus for nuclear spectrometry were also set forth.
双核处理器相当于把两个大脑整合在一个芯片上。
本文介绍一种USB2.0设备控制芯片IP核的设计，并且主要对其中的主控制器的设计进行介绍。
This thesis introduces the design of USB2.0 IP CORE for USB device controller, and mainly about the design of the main controller of the IP CORE.
该方法已应用到实际系统，并对其他基于ARM 7tdm I核的芯片应用也具有指导意义。
This method has been used in a practical system, other chip application based on ARM7TDMI would be carried with guidance of this method.
通过建立SDH芯片验证平台和SDH芯片测试平台，实现IP软核的功能仿真、时序仿真和芯片性能测试。
With the establishing of verification and test platform for SDH chip, We realize the function simulation, timing simulation and performance test of the IP soft-core.
该系统主要采用小灵通基带芯片ML7338（ARM7TDMI核）和RDA5206射频模块，实现对射频信号的解调，同时对基带信号重新编码再调制发射，很好地解决了普通直放站射频干扰问题。
The ML7338(ARM7TDMI core) and RF module RDA5206 are used to demodulate RF signals, recode, remodulate and transmit baseband signals, thus solving the RF interference problem in traditional stations.
从可测性设计角度讨论了信息安全处理芯片的芯片级测试控制器的设计以及相应核的可测性设计。
The design of chip test controller of a security chip and design for test of corresponding cores are discussed in detail.
对照数据手册的时序要求优化硬件逻辑设计，解决了双核嵌入式处理器TMS320 VC 5471和USB芯片PDIUSBD12时序不兼容的问题。
We have optimized the hardware logic according to the timing requirement on datasheet, and solved the timing incompatibility between the dual-core processor TMS320VC5471 and the USB chip PDIUSBD12.
本文围绕媒体处理器IP核在媒体系统芯片中的重用，对数据通路设计及控制信息通信机制进行研究。
The paper studies the design of data paths and the communication mechanism of control information, focusing on the reuse of media processor IP core in media SOC.
媒体处理器IP核重用成为可编程媒体系统芯片设计的重点和难点。
The reuse of multimedia processor IP core is the key and difficulty of programmable media SOC design.
而就芯片而言，诺加雷特博士打算利用电子而非原子核的自旋。
In chips, Dr Nogaret proposes to use the spin of the electron rather than the spin of the atomic nucleus.
系统级芯片(SOC)的设计大多采用以ip核为主的预定制模块，IP核已经成为未来主流芯片设计的核心构件。
Preorder module IP core is widely used in the design of System on chip (SOC), IP core is becoming the kernel component in the designing of future chip.
该芯片有两个核，一个US B核和一个8051核。
该芯片有两个核，一个US B核和一个8051核。
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