JW认为下一个十年将会兴起的另一个架构是，连接企业资源到云的网络是一个单芯片上的总线。
Another architecture, that JW sees coming in the next 10 years is the one where "the network connecting enterprise resources to the cloud is a bus on a single chip."
增强的总写架构-目前64位芯片上的总线架构比前几代更加的快也更加的广。
Enhanced bus architecture - The bus architecture on current 64-bit chipsets is faster and wider than earlier generations.
本论文的主要工作即着重于系统芯片中片上总线结构的性能评价研究，包括总线结构的建模、系统仿真环境的建立以及性能评价的方法。
This paper focuses on performance estimation of the embedded microprocessor based on the on-chip bus, including on-chip bus modeling, high-level simulation environment building and their combination.
其核心思想是将计算机网络技术移植到芯片设计中来，从体系结构上彻底解决总线架构带来的问题。
The core idea is to transplant the knowledge of network technology of computer into the design of chips such that systematically solves the problems due to bus architecture.
论文的重点是在FPGA芯片上实现各个总线控制器以及相互之间的数据转换。
The paper focuses on realizing each field bus controller and the mutual data conversion on FPGA chips.
介绍了USB总线接口芯片CH375，并在此基础上实现了PC与嵌入式医疗设备的USB通讯，给出了相关的程序代码。
This paper presents CH375 bus interface chips, the USB communication between PC and embedded medical equipment, and the relative procedure code.
在对PCI协议芯片工作过和应用特点进行深入分析的基础上，设计出基于PCI总线的数据采集卡。
After analyzing the working principles and features of PCI protocol chip, we design a higher speed data acquisition card.
介绍了几种新型的视频转换芯片在机载计算机系统上的应用，主要包括PAL制视频和低电压差分信号(LVDS)视频总线设计。
This paper lays particular stress on new video chips for airborne application, mainly on PAL video and LVDS bus design.
各个节点设计上采用内置CAN模块的飞思卡尔16位单片机作为主控芯片来搭建硬件电路，以实现CAN总线的物理层和数据链路层。
Through using 16-bit freescale MCU embedded CAN controller as master chip in each node, it achieved the design of hardware circuit, so realized CAN physical layer and CAN data link layer.
最后，在研究EP -H31580 1553总线芯片的基本功能和读写时序的基础上，完成了1553总线模块的硬件设计。
At last, 1553 bus circuit design has been finished on the basis of studying the basic function and timing of 1553 chip EP-H31580.
在分析IIC总线协议的基础上，文中详细叙述了DM 642通过IIC模块对视频编解码芯片的寄存器进行配置、校验的流程。
IIC bus protocol analysis on the basis of a detailed description in the text adopted by the IIC module DM642 video decoder chip register configuration, calibration process.
在分析IIC总线协议的基础上，文中详细叙述了DM 642通过IIC模块对视频编解码芯片的寄存器进行配置、校验的流程。
IIC bus protocol analysis on the basis of a detailed description in the text adopted by the IIC module DM642 video decoder chip register configuration, calibration process.
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