本文提出了采用模拟多路开关的模拟内建自测试电路abist的一种新结构。
This paper presents a new structure of analog Built - in Self - Test circuit (ABIST) consisting of analog multiplexers.
另外，本文还针对IP核投片测试提出一种扫描测试电路结构，能够实现测试芯片的扫描测试和高速内建自测试(BIST)。
Moreover, a scan test circuit was proposed. This circuit can implement scan test and high speed build in self test (BIST) for IP core chip tests.
针对混合信号电路的测试问题，提出了一种内建自测试(BIST)结构，分析并给出了如何利用该结构来计算片上高速模数转换器(adc)的静态参数。
Aiming at the mixed-signal circuit testing, an integrated built-in self test (BIST) architecture for testing on-chip high speed ADC was presented.
提出了一种在内建自测试(BIST)中进行部分扫描的算法，此算法综合了电路的结构分析和可测性分析。
A partial scan algorithm for BIST, which combines the structure analysis and testability analysis, is presented in this paper.
通过添加测试引脚、设计专用测试模式，内建自测试等方法有效的解决了该芯片电路的功能测试和电气性能测试。
The top metal test pad, special test mode and BIST are adopted in the IC circuits to solve the IC test problem about the chip function test and electric character test.
内建自测试作为一种新的可测性设计方法，能显著提高电路的可测性。
As a new method of design for testability build-in self-test can prominently improve the testability of the circuits.
桥接跨电路的桥接方式是在将一根来自测试设备的测试线或来自其他电路的导体放入另一个电路的一个导体中。
Bridging across a circuit is done by placing one test lead from a test set or a conductor from another circuit and placing it on one conductor of another circuit.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
文中首先介绍了内建自测试的实现原理，在此基础上以八位行波进位加法器为例，详细介绍了组合电路内建自测试的设计过程。
The BIST of the principle of achieving is introduced first in this paper, then take the 8-bit ripple carry adder as an example, describes the design process of BIST.
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