本文将分析并讨论脉动与波前阵列处理器的算法、结构和应用。
This article provides a general analysis and discus sion of the algorithms, structure, application perspectives of VLSI array proces sots, including Systolic and Wavefront.
研究了一类多重循环算法的线性脉动阵列实现。
The realization of mapping a class of nested loop algorithms to linear systolic array is studied.
此外，为该算法设计出脉动阵列VLSI结构，并和现有结构进行了对比分析。
The systolic VLSI was designed to perform the new algorithm, followed by complexity analysis.
采用离散占空比控制技术的直接转矩控制能够在减小输出转矩脉动的同时保持算法简单的特性。
Applying discrete duty ratio control technology into direct torque control can reduce the ripple, and keep the feature of simplicity.
在FPGA上实现大规模脉动式阵列对双序列比对算法进行加速能够大幅度提高比对的效率。
Implementing large scale of systolic array in FPGA to accelerate pare-wise alignment can improve the efficiency of alignment remarkably.
文中提出了两个新的脉动阵列算法，用以阐述理论结果对复杂问题的应用。
Two new systolic arrays for Deconvolution and Eigenvalue problems are included to illustrate the use of our theoretical results.
本文应用自适应最小二乘格型（LSL）算法估计非恒定流压力脉动的功率谱密度。
This paper uses the adaptive least squares lattice algorithm (LSL) to calculate the spectral estimation of pressure fluctuations in unsteady flow, and describes the principle of the LSL algorithm.
采用基于BP神经网络整定的PID控制策略以减弱系统的耦合影响，并给出了其控制算法在FPGA上实现的方法，包括脉动阵列算法映射、数据表示及精度和运算部件设计。
A control strategy based on BP-PID was introduced to decouple the looper system by using FPGA, which includeds systolic mapping, data representation and precision, and computation components design.
该结构将波前控制算法分为递归运算和卷积运算两部分后，采用规范映射方法将其分别映射到脉动阵列，再将两个阵列链接以实现单路的波前控制运算。
This structure divides wavefront control calculation into recursive algorithm and convolution algorithm, and maps them to respectively systolic array by using canonical mapping method.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
同时为了降低FPGA的资源占用，RSA算法采用流水线方式实现脉动阵列，并通过软硬件的协同合作完成算法中素数的判定生成算法参数。
To reduce the resource used by RSA algorithm, systolic array is accomplished by pipelining and the parameter is generated by software cooperated with hardware.
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