探讨了PC的串行接口用于光电编码器的脉冲计数和伺服电机控制两种非通信功能的应用。
The COM of IBM-PC applications for the counter of Opt-encoder pulse and the controller of AC -Servo are study in this paper.
全部都可以用来识别和监测电机的速度或确定编码器脉冲计数。
All can be used to identify and monitor motor speeds or determine pulse counts of encoders.
软件由动态显示模块、脉冲计数测速、脉冲捕获测速和系统通信组成。
The software is composed of modules such as the dynamic display, pulse counting and pulse capture and communications of system.
外壳可同时终了轴和通轴固定件和加工的普遍容纳所有传感器模块，无论所需的脉冲计数。
The enclosure accommodates both end-of-shaft and thru-shaft mountings and is universally machined to accommodate all sensor modules, regardless of the desired pulse count.
新版本支持环境传感器和脉冲计数传感器，它将多个一体化的系统管理传感器统一到同一个无线网络。
The new version includes support for environmental sensors and pulse-count transmitters, enabling the integration of multiple building management sensors into the same wireless network.
有手动复位和电气输出信号的脉冲计数器。
文章介绍的是采用由高速脉冲计数器、PL C和光电增量编码器构成的位置环控制系统。
The article expound a kind of position control system that is made up of high speed pulses counter, PLC and light cell code device.
然而，脉冲计数的准确性受到很多因素的影响，分析认为主要是由外界电磁干扰和多斑点的产生引起计数的不准确。
But, the accuracy of the count is affected by many factors, mainly by the interference of the external electromagnetic waves and the generation of the multi cathode spots.
瞬时转速测量的主要误差为晶振脉冲计数误差和转角计量误差。
It is shown that the error of transient engine speed measurement comes from both the time interval counter and crank angle measure.
门控脉冲计数有闸门与计数器分开和一体两种方式。
Pulse counting with gate controlling have been two counted modes that the gate with counter are divided or combined.
本文详细的介绍了等效脉冲计数法和改进等效脉冲计数法的软件以及硬件实现。
In this paper, the software and hardware achieved of equivalent pulse counting and improved equivalent pulse-counting method are described in detail.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
本文设计的CPLD芯片的算法，采用两级脉冲计数及CPLD硬件延时方法，以达到CPLD资源占用和功能实现的平衡。
The algorithm of CPLD chip designed in this paper, using two pulse-counting and CPLD hardware delay means to achieve the balance between CPLD resource consumption and function.
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