将磁心存储器读出放大器的输出选通到寄存器的触发器中的一种脉冲。
A pulse to gate the output of a core memory sense amplifier into a trigger in a register.
用一低通滤波器和施密特触发器排除高频噪声脉冲。
Removing high frequency noise pulses by a low-pass filter and Schmitt-trigger.
该晶闸管触发器采用集成运数放大器，移相触发脉冲的形成是根据三相交流电的各相与移相控制电压直接比较原理实现的。
The shift trigger pulse of the thyristor trigger circuit with integration amplifier is generated by comparing directly principle of three-phase AC and shift-phase control voltage.
本文利用四值逻辑讨论了触发器的逻辑功能，并讨论四值逻辑在脉冲异步时序逻辑网络分析和设计中的应用。
This paper has discussed the logic behaviour of flip-flops using the four valued logic and its applications in the analysis and design of pulsed asynchronous sequential logical networks.
试验结果表明，以该触发器为控制核心的脉冲信号发生与控制装置具有结构简单、调节方便、性能可靠、造价低等特点。
The test results show that the pulse signal generate and control device based on this type of trigger has characteristics of simple, easier operation, higher precision, lower cost and so on.
开关管冲击耐压装置由高压脉冲产生器、击穿检测器、触发器，及自动控制器、DC/AC变换器等构成。
The high voltage endurance test device for switch tube is composed of high voltage pulse generator, high voltage breakdown detector, trigger, auto-controller and DC/AC converter.
系统内设计了高分辨率的数字触发器和高精度的同步中断脉冲以及高精度快速的A/D转换，实现了数字化高性能调节控制系统。
It is a high performance digital controller, which possesses a high resolution digital trigger, high precision synchronous interrupt pulses, and a high precision fast A/D converter.
应用一个负的触发器脉冲在一个定时周期内来同时复位和触发，这样使电容器C放电并且重新初始化一个循环，从复位脉冲的正边开始启动。
Applying a negative-going trigger pulse simultaneously to RESET and TRIG during the timing interval discharges C and reinitiates the cycle, commencing on the positive edge of the reset pulse.
详细地介绍了可控硅整流器(SCR)线型触发器的改进型设计方案，提出了用于高脉冲重复频率的双极晶体管触发器的实用新电路。
An improved plan of silicon controlled rectifier (SCR) line type trigger is described in detail. Anew practical circuit of bipolar transistor trigger for high pulse repeat frequency is presented.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。
Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock.
可以使用箝位电路替代Schmitt触发器净化高频输入脉冲。正反馈放大器是信号级脉冲…
You can use a clamping circuit instead of a Schmitt trigger to clean up…
可以使用箝位电路替代Schmitt触发器净化高频输入脉冲。正反馈放大器是信号级脉冲…
You can use a clamping circuit instead of a Schmitt trigger to clean up…
应用推荐