有些脉冲星表比地球上最精确的时钟还准。
Some pulsars keep time better than the Earth's most accurate clocks.
你的方法取决于你的项目是只需要那块电子脉冲发生器，还是带有指针，可以继续报时的时钟。
Your surgical procedure will depend on whether your project just needs the electronic pulse generator. or a clock with working hands that continues to tell time.
这就是移位寄存器，因为数据在每一个时钟脉冲的作用下通过寄存器会移动一位。
It is called a shift register because the data is shifted through the register by one bit position on each clock pulse.
在收到停止位之后，设备将通过拉低数据线，生成最后一个时钟脉冲来应答收到的字节。
After the stop bit is received, the device will acknowledge the received byte by bringing the Data line low and generating one last clock pulse.
“激光脉冲轻拍壳层产生了像铃声一样声音”，国家标准和技术研究所的物理学家Till Rosenband说，现有的量子逻辑时钟是由他开发的。
"With a laser pulse, you can tap that shell and make it ring like a bell," said physicist Till Rosenband of NIST, who built the existing quantum-logic clock.
关键是为了使用时钟DLL，它不只是最小化时钟脉冲相位差，还提供双倍输出的时钟频率。
The trick is to use a clocked DLL, which not only minimizes clock skews, but also offers a double-frequency output clock.
每当计数器被时钟脉冲触发一次时，计数器输出的二进制数便累减1。
The counter output, which represents a binary number, decreases by 1 any time the counter is triggered by a pulse .
在二进制位同步通信中，使用时钟脉冲来控制数据和控制字符的同步。
In binary synchronous communication, the use of clock pulses to control synchronization of data and control characters.
一般采样脉冲都是在装置内部时钟的控制下产生的。
Generally sampling pulse is produced by the control of clock inner device.
这些功能的实现是通过系统中电控部分的电源、时钟、存储、超声波脉冲信号发生、处理、温度采集、串行通信电路实现的。
These functions are realized by the circuits of power, clock, memory, ultrasonic pulse signal occurs and handle, temperature gathered and serial communication in system.
对于数据和时钟脉冲列之间的相关延迟的模拟，以0.1微秒为递增单位增加到3.1微秒。
Simulation of relative delays between Data and Clock pulse trains in 0.1 microseconds increments to 3.1 microseconds.
在脉冲发生器输出端后加一级驱动电路，再接入计数器的时钟脉冲源输入端，可有效地避免通常发生在实验过程中计数器不规则的跳变。
To use the way of put a driven circuit behind the pulser, lead through the input of count clock pulse, can avoid the irregular date on the counter during experiment effectively.
被称为时钟的定时器释放出准确定时的电子信号，为处理器的工作提供规则的脉冲。
Is called the clock timer release of accurate timing of electrical signals, pulse provides rules for processor work.
阿计时器所谓的时钟精确定时发布电信号，提供定期脉冲处理器的工作。
A timer called clock releases precisely timed electrical signals that provide a regular pulse for the processor's work.
GPS接口板通过软件方式实现实用化的守时钟，降低对单个PPS秒脉冲的依赖性。
Through the software the practical watching clock for interface module of GPS is implemented and the dependence on the PPS pulse is reduced.
对于双刻度弧线时钟，我通过一个基本型微处理器将脉冲送到电动机。
I send the pulse to the motor through a BASIC Stamp microprocessor. which keeps track of the time.
激光时间传递是通过激光脉冲在空间的传播来实现地面与卫星时钟或地球上远距离两地时钟的同步。
Time transfer by laser pulses is based on the propagation of light pulses between satellite and ground clocks or between remote clocks on THC Earth.
提出从接收到的光信号脉冲串中提取光基频时钟的方案。
A novel all optical scheme for extracting clock pulses with basic frequency from the receiving non uniform OTDM optical signal is proposed.
本文介绍了一种利用计算机时钟脉冲细分光栅脉冲信号相位的方法——改进型时钟脉冲细分技术。
A method for subdividing the grating pulse signal by means of using computer clock pulse is presented in this paper.
每来一个时钟脉冲，N位加法器将频率控制数据m与相位寄存器输出的累加相位数据相加，并将结果送相位寄存器输入端。
Frequency controlled data (m) plus an accumulative phase data output by a phase register in an N-bit adder when a clock pulse comes, the result is sent to the input port of the phase register.
一个称作时钟的计时器准确地发出定时电信号，该信号为处理器工作提供有规律的脉冲。
A timer called a clock releases precisely timed electrical signals that provide a regular pulse from the processor's work.
为减少全光时钟提取中的码型效应，设计了混码器对注入数据脉冲进行预处理。
To reduce the pattern effect in all-optical clock recovery, a novel device termed as code mixer was designed to preprocess the injected data signals.
但是，新型基站利用GPS，可充分发挥卫星发射的高精度时钟脉冲。
But new cell stations use GPS to take advantage of the highly accurate clock pulses transmitted by satellites.
系统硬件部分包括GPS接收机、GPS时钟模块、脉冲峰值采集卡及工控机。
The hardware includes GPS receiver, pulse peak acquisition card, GPS clock module and industrial computer.
当基准和反馈时钟信号的相位和频率相同时，PLL处于锁定模式，且PFD输出信号中不生成脉冲。
When the phase and frequency of the reference and feedback clock signals are the same, the PLL is in lock mode, and the PFD does not generate pulses in its output signals.
在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。
Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock.
触发器的并行加载可以是同步的(即在时钟脉冲到达时发生)或异步的(不依赖于时钟)，这取决于移位寄存器的设计。
The parallel loading of the flip-flop can be synchronous (i. e., occurs with the clock pulse) or asynchronous (independent of the clock pulse) depending on the design of the shift register.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
逻辑控制电路设计：D触发器、不重叠时钟脉冲发生器等模块的设计。
Logical control circuit design: this part includes the design of DFF, non-overlap clock generate and so on.
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