在芯片规模指数式上升和要求面市时间快速缩短的双重压力下，验证已成为数字集成电路设计的瓶颈。
Under pressure of the increase of chip scale and the decrease of timing to market, verification has become the bottleneck of digital IC design.
在芯片规模指数式上升和要求面市时间快速缩短的双重压力下，验证已成为数字集成电路设计的瓶颈。
Under pressure of the increase of chip scale and the decrease of timing to market, verification has become the bottleneck of digital IC design.
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