最后，在综合了以上研究的基础上，实现了H。263视频编译码软件的实验系统。
At last, based on the integration of the upwards research, we realize the H. 263 video encoding and decoding software experiment system.
所实现的编译码器能对BCH(23,12)码进行正确地编码和译码，能纠正小于或等于3位的随机错误。
The encoder can correctly encode and decode the BCH (23, 12) code which can correct less than or equal to 3 bit error.
这些内容对于LDPC编译码的实现有一定的指导意义。
说明：根据BCH码的编译码原理，用C语言实现的BCH码编译码过程，并进行误码率分析。
According to the principle of BCH code , the program will realize the encodeing and decoding of BCH code, the analysis of BER.
这些特殊结构的LDPC码不仅可以压缩编译码所需的矩阵储存空间，而且还能有效的降低编码复杂度，这对工程上实现LDPC码的应用具有重要的意义；
These quasi-cyclic LDPC can not only reduce the storage of LDPC generator matrix, but also decrease the encoding complexity efficiently, which is of great significance for the applications.
并详细介绍了用FPGA实现该编码方案的方法，包括BCH码的编译码和交织编码。
An FPGA implementation method of this scheme is presented, including BCH encoder and decoder and the interleaver.
首先介绍了H . 263建议中视频信号纠错编码的应用，然后着重介绍了BCH(511,493)纠错编译码的设计及其实现。
After a brief description of error correcting code of applied digital video signals in H. 263, this paper focuses on the design and implementation of BCH (511,493) error correcting code.
基于CPLD设计了一种能实现该种转换的HDB3码编译码器。
Based on the CPLD, a circuit of HDB3 CODEC is designed in this article to realize this transform.
方便地实现了光学全息编码保密性强的特点，免去了光学全息编译码所需的制作全息图的实验设备。
With the method there is the advantage of optical hologram's information encoding without any kind of optic equipments.
给出一种用单片机系统进行曼彻斯特编译码，实现多路测井数据传输的技术方案。
This paper presents a technical method of Manchester coding and decoding by single-chip microcomputer with software to implement logging data transmission of multiple channals.
经测试，整个编译码算法的实时实现共用去27.91MIPS。
A total 27.91MIPS is comsumed to implement the algorithm of G.
码率可变的RCPT码能够实现这样的编码要求 ，但是 RCPT码的编译码性能取决于其删除矩阵的选取 。
The RCPT code can fulfill such requirement, while the performance of RCPT code lies on how we choose the puncture table.
仿真结果表明，该乘法器结构规则、易于实现、消耗资源少、性能良好，为实现RS（255，223）编译码奠定了基础。
The multipliers have regular structure and can be easily realized, which consume less resource and perform well. They are the basis of RS(255,223) encode and decode.
提出FPGA可实现的TPC编译码模块整体设计方案，并结合现有AHA公司的AHA4501芯片，进一步对TPC译码性能进行了验证。
The overall TPC decoding module design using FPGA, combined with existing AHA4501 chip, and further verify the performance of TPC decoding.
提出FPGA可实现的TPC编译码模块整体设计方案，并结合现有AHA公司的AHA4501芯片，进一步对TPC译码性能进行了验证。
The overall TPC decoding module design using FPGA, combined with existing AHA4501 chip, and further verify the performance of TPC decoding.
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