设备列表没有列出高精度音频(HDA)编码译码器。现在，OSS支持所有HDA编码译码芯片和控制芯片。
High Definition Audio (HDA) codecs are not listed in the device lists. At this moment OSS supports all HDA codec chips and controller chipsets.
PackageKit寻找合适的编码器和译码器，如果你同意，就会自动被安装。
PackageKit then looks for the appropriate codec and, if you approve, installs it.
你不需要知道编码器和译码器在哪里，你不需要搞清楚细节，这些PackageKit会帮你做好。
You don't need to know where the codec is, you don't need to fiddle with the details, PackageKit does it all for you.
真正打动我的是PackageKit能够自动识别你的媒体播放器不知道如何播放的编码器和译码器。
What really impressed me was that PackageKit now automatically recognizes when you run into a media codec that your media player doesn't know how to play.
XML是标准语言，很容易为它编写编码器和译码器。
XML is a standard language, and it is very easy to write encoders and decoders for.
如何使一个简单的编码器和译码器吗？
文章研究多用户MIMO下行链路中线性预编码器和译码器的联合优化问题。
This paper deals with the joint optimization of linear precoders and decoders for multiuser MIMO downlinks.
所实现的编译码器能对BCH(23,12)码进行正确地编码和译码，能纠正小于或等于3位的随机错误。
The encoder can correctly encode and decode the BCH (23, 12) code which can correct less than or equal to 3 bit error.
接着介绍了R S码的编码原理和时域迭代译码算法，在此基础上设计实现RS码编码器和译码器。
Then, the code theory and time-domain iterative decode algorithm of RS code is introduced, RS coder and decoder are designed and implemented in this base.
作为一个例子，论文通过给出最小熵译码器所对应的先验一般信源，揭示了其通用编码的原理。
As an example, we explain the principle of the minimum entropy decoder by finding its corresponding apriori general source.
另外针对光纤通信系统对传输信号码型的要求，利用FPGA设计了8b10 B编码器和10b8 B译码器。
In addition, 8b10b encoder and 10b8b decoder are designed on base of FPGA for meet with the need for the type of transmission data in fiber communication system.
利用多级离子注入技术，一种新型的CMOS四值译码器与编码器被设计。
By using the multiple ion implantation technique, novel CMOS quaternary decoder and encoder are designed.
所述编码器组件（1）分别接向转向开关（2）、组合变光开关（3）、译码器组件（4）和（14）、蓄电池组（13）和地。
The encoder assembly (1) is respectively connected with a change-over switch (2), a combining beam switching control (3), the decoder assemblies (4) and (14), a storage battery (13) and the ground.
该编码器和译码器适合用于高速率的现代通信技术，特别是硬件资源较丰富的环境。
The encoder and decoder is optimized for high-speed modern communications technology, particularly in the higher hardware resources environment.
本论文设计的是RS(204,188)码的编码器和译码器，最多能纠正8个错误。
In this paper, rs (204,188) encoder and decoder is designed, which can correct 8 errors to the maximum.
指令译码器将编码指令信号进行译码，最后由驱动电路来驱动执行电路实现各种指令的操作。
Encoding instruction decoder for decoding command signals, and finally by the drive circuit to drive the implementation of circuit operation to achieve a variety of commands.
用FPGA设计并实现了标准中码长16200，码率2/3IRA码的编码器，且设计出相应的译码器结构。
The encoder of length 16200 and rate 2/3 IRA codes is designed and implemented with FPGA, and the corresponding decoder structure is designed.
编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。
Encoder and decoder is a basic computer circuit devices. This Curriculum design by EDA design encoder and decoder.
程序的主要功能是利用哈夫曼编码对数据进行无损压缩，实现Huffman压缩的编码器和译码器。
The main functions of the procedure is to use Huffman coding lossless compression of data to achieve Huffman compression encoder and decoder.
编码器由8线- 3线优先编码器作为实例代表，译码器则包含3线- 8线译码器和2线- 4线译码器两个实例模块组成。
Encoders from 8-3 priority encoder for example, and decoder includes 3-8 decoder and the 2-4 examples of the two decoder modules.
编码器由8线- 3线优先编码器作为实例代表，译码器则包含3线- 8线译码器和2线- 4线译码器两个实例模块组成。
Encoders from 8-3 priority encoder for example, and decoder includes 3-8 decoder and the 2-4 examples of the two decoder modules.
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