只有一个输入的数字电路单元是缓冲器或反相器，而输入在一个以上的则称为逻辑门。
Only one input of the digital circuit unit is the buffer or inverter, the input in more than one are called logic gates.
如果设置为1，调制解调器将接收数据并存入缓冲区，直到单元同步。
If set to 1, the modem will accept data and buffer it until the unit is synchronized.
此限幅放大器由输入缓冲、主放大单元、输出缓冲、偏置补偿电路四部分组成。
This limiting amplifier composed of an input buffer, amplifier cells, output cells, and offset cancellation circuit.
改进的输入缓冲方案是在AT M交换单元的输入队列和仲裁逻辑之间加入一个准随机存储器。
The improved model of input buffer presented is to insert a quasi random memory between input queue and arbitration logic at ATM switching unit.
耐克公司在鞋跟响应缓冲放大单元。
根据时分立体成像原理，提出了双缓冲快速刷新图像的方法，研制出微操作系统的显微立体成像单元；
According to time-sequential imaging techniques, a way of double buffer image refreshing is put forward, the micro stereoscopic imaging system is developed.
其中包括地址缓冲、译码器、存储单元、灵敏放大器和输出缓冲电路。
The crucial path includes address buffer, decoder, memory unit, sense amplifier and output buffer.
运算器：运算器是数据加工处理部件，它是由算术逻辑单元(alu)、累加器、数据缓冲器等组成。
Arithmetic unit: arithmetic unit is a data processing unit that consists of arithmetic logic unit (ALU), accumulator, data buffer, ect.
Kellas先生设计的机械缓冲装置在蜂窝结构的每个单元的结合部都有灵活的铰链连接。
The mechanical cushioning system that Mr Kellas has designed has flexible hinges at the junction of each cell in the honeycomb.
集中处理信元缓冲的AT M交换机结构复杂、扩展性不好、不易保证高吞吐率，而由多级交换单元分布处理信元缓冲可克服这些缺点。
There are some drawbacks in ATM switch unifying buffer: complicated structure, lack of expansibility and difficulties in ensuring to ensure high throughput.
重点描述了安全控制单元中杀毒软件的集成和升级，并实现了对缓冲区中数据的病毒扫描。
Mainly describes the integration and the update of anti-virus software on the security control units and realized the virus scanning on data of buffering area.
纸浆模塑结构单元的缓冲性能与其单元厚度及承载边边长成正比。
Buffer function and its unit thickness and loading side side of the pulp mold Su structure unit grow up a direct proportion.
在弯曲处理过程中，弯曲缓冲间隔件(42)使弯曲容易进行并且极大地保证了芯单元的性能。
During the bending processing, the bending buffer distance piece (42) can easily realize the bending and greatly ensures the performance of the core unit.
每一个处理模块都可以包括网络接口、至少一个缓冲器、分组解析器、分组构造器和至少一个处理单元。
Each processing module may include a network interface, at least one buffer, a packet parser, a packet builder, and at least one processing unit.
这先进先出接收机接收缓冲区写在输入数据速率的内存填补其中的数据存储单元。
This FIFO receiver buffer receives data at an input write-data rate filling up the memory storage cells therein.
各功能模块的设计，包括桥选择单元、MLB从状态机、缓冲区、AHB主状态机，仲裁器；
The design of each functional module, including the bridge selected module, MLB slave state machine, buffer, AHB master state machine, arbiter.
储存单元、电流检测器、施密特缓冲器、反相器1、反相器2依次相连接。
The storage unit, the current detector, the Schmidt buffer, the inverter (1) and the inverter (2) are connected in sequence.
优选的是，浪涌电流限制器设备进一步包括可充电电容缓冲器，其设置在关于基于IGBT的限制器单元的下游，用于形成缓冲的输出。
It is preferably, that the inrush current limiter device further comprises a chargeable capacitive buffer, arranged downstream in regard to the IGBT-based limiter unit for forming a buffered output.
这意味着，依赖于缓冲器的填充状态和负载的操作模式，基于IGBT的开关单元从一个位置切换到另一位置。
That means the IGBT-based switch unit switches from one position to the other depending from the filling status of the buffer and the operation mode of the load.
有限元模型包括5个节点和5个单元，这些单元分别是直流电机单元、齿轮减速器单元、梁单元、曲柄单元和缓冲器单元。
The whole finite element model includes 5 nodes and 5 elements, and these element types are D. C. motor element, reduction gear element, beam element, crank element and buffer element.
该电容DC缓冲器用作高频去耦单元，并且由对应的电容器形成。
The capacitive DC buffer serves as a high frequency decoupling unit and is formed by a corresponding capacitor.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
FPGA实现MV B控制器功能，分为曼彻斯特编码器、解码器、缓冲区、中央控制单元、内部存储器和单片机接口等几部分。
The FPGA is designed as a MVB controller which consists of Manchester encoder, Manchester decoder, buffer, center control unit, internal memory, MCU interface and so on.
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