随着集成电路工艺与技术的飞速发展，集成电路已经进入系统级芯片阶段。
With the rapid development of semiconductor technology, integrated circuit has stepped into a new era of SOC.
介绍了系统级芯片的定义、优点、构成要素、设计原则、品种和目前存在的问题。
The definition, merits, essential factor to constitute, principle to design, variety and existent problem at the moment are introduced.
随着数据吞吐量不断上升以及系统低功耗要求，系统级芯片对存储器的需求越来越大。
With the increasing demand for large data throughput and the requirement of lower system power consumption, the embedded memory demand is increasing rapidly.
在系统级开发的过程中需要优先解决可测性问题，特别是设计系统级芯片会用到很多数字线路和IP内核。
In the process of system developing, the engineer should first solve the problem of DFT, especially when lots of digital circuits or IP cores are used in system On Chip.
针对传统系统级芯片动态内存管理单元(SOCDMMU)，提出用软件方法实现SOCDMMU中的核心部件。
Aiming at traditional System on Chip Dynamic Memory Manage Unit (SOCDMMU), this paper proposes realizing the core parts of SOCDMMU with the software method.
系统级芯片(SOC)的设计大多采用以ip核为主的预定制模块，IP核已经成为未来主流芯片设计的核心构件。
Preorder module IP core is widely used in the design of System on chip (SOC), IP core is becoming the kernel component in the designing of future chip.
论文针对目前大规模集成电路设计要求，结合电力电子应用，设计了一个SPWM信号产生系统IP软核，该软核可广泛应用于系统级芯片设计中。
According to the requirement of the VLSI and the wide application of power electronics, IP soft core of SPWM generation system is designed. And it can be widely applied in system level chip design.
本实验平台采用CYGNAL公司的一款完全集成的混合信号系统级芯片C 8051f 320作为主控芯片，同时采用AT 89 C51单片机作为可控硅触发板的控制芯片。
This platform USES C8051F320 device of CYGNAL as main control chip which is fully integrated mixed-signal System-on-a-Chip MCUs, and AT89C51 MCU as silicon control triggering control chip.
通过嵌入处理器芯片的光通信，建立Exaflop(1018次，是千万亿次petaflop的1000倍)级水平的高效能计算机系统的愿景将在不太遥远的未来实现。
With optical communications embedded into the processor chips, the prospect of building power-efficient computer systems with performance at the Exaflop level might not be a very distant future.
这些手机都将采用Android 2.2系统或是其2.3升级版，配有4.3英寸显示屏以及双核处理器（摩托罗拉的DroidBionic甚至还配有NVIDITegra2的芯片）。
These devices all run Android 2.2, with likely upgrade or launch with Android 2.3, have 4.3 inch displays, and dual-core processors (the Droid Bionic even has the NVIDI Tegra 2 chip).
随着半导体技术和电子设计自动化（EDA）的迅猛发展，使系统级可编程芯片（SOPC）成为可能。
The tremendous development of semiconductor technology and electronic design automation (EDA) made the system on a programmable chip (SOPC) possible.
作为虚拟特征生成实例，本文以电子设备概念设计为例，详细介绍了系统级和芯片级的虚拟特征生成方法。
As examples of VFG, this paper introduces in detail the system - and chip-level VFG of electronic devices.
随着集成电路工艺的飞速发展，人们已经可以将原先的板级系统集成在一块芯片上，系统芯片逐渐成为集成电路设计的主流发展趋势。
With the development of semiconductor process technology a system on a PCB (Printed Circuit Board) which is composed of several ICs can be integrated into a chip.
深亚微米和纳米级的半导体技术迅速进步，使得集成电路的设计已经进入系统集成芯片时代。
The rapid progress of semi-conductor technology on deep sub-micro and nanometer scale announces the SOC era of IC design.
MPEG4编解码芯片包含了复杂的算法，利用系统设计语言建立事务级的参考模型已经非常有必要。
The MPEG4 encode and decode module include complex algorithm , so it is very necessary to build a transaction level reference module .
根据铁路车号自动识别的基本原理，采用ARM9工业级芯片AT91SAM9260设计开发了铁路车号识别系统的嵌入式系统；
The train identification system based on embedded system is designed with ARM9 RSIC CPU AT91SAM9260 under the principle of automatic train identification system.
针对巨型机概念设计需求，在传统芯片级与系统级布局规划方法基础上，提出一种面向并行设计规划的快速布局模型与算法。
Based on the traditional placement methods at VLSI and system level, a novel model and algorithm of rapid system level placement for CDP is presented.
设计中选择了两优先级轮转仲裁算法，以提高系统性能；优化了状态机编码方式，以减小芯片面积和降低动态功耗。
In this design, a 2-level round-robin arbitration algorithm is chosen to improve system performance, and state machine coding style is also optimized to reduce chip size and dynamic power consumption.
其设计的优劣直接影响着FPGA实现具体设计的性能及FPGA芯片可以承载的最大系统级晶体管数。
The quality of the block's design directly effects the performance of the FPGA and the maximum system gates that FPGA included.
它们所提供的解决方案极大地方便了芯片级、板级、系统级及数字网络的测试。
The standards provide more solutions to the test of IC level, board level, system level and digital networks, which facilitate the debugging and testing of them.
公司能够并且已着手将其三种产品工艺中的任意两种或全部三种集成到一块单片芯片之上，以实现功能强大的系统级解决方案。
The company can and does combine any two or all three of its product disciplines into a single monolithic chip to deliver powerful system-level solutions.
公司致力于芯片热源应用的研发和生产。2003年，公司斥资在中国境内温州国家级高新技术产业园区拓展生产。其中主要有地热系统，芯片热水器系列等家电产品。
In 2003, our company invest to expand produce in Wenzhou nation Hi-tech industry park in ChinaMain product is earth heat system, chip heat water machine etc home appliance.
本文的主要贡献在于提出了多核系统芯片任务级自动并行化的研究方案和系统实现。
The main contribution of the thesis is to address the issue of automatic task-level parallelization for the architecture of MPSOC and to give the system implementation.
论文从系统级、模块级、电路级和物理级对非挥发性存储器芯片设计中的关键设计技术进行了研究。
In this paper, we design this non-volatile memory chip in system level, module level, circuit level and physical level.
论文从系统级、模块级、电路级和物理级对非挥发性存储器芯片设计中的关键设计技术进行了研究。
In this paper, we design this non-volatile memory chip in system level, module level, circuit level and physical level.
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