时钟树综合是芯片后端设计至关重要的一环，时钟偏差成为限制系统时钟频率的主要因素。
Clock Tree Synthesis is important in the backend-end design of chip design, and the clock skew has become the major part of constraints that limit system clock frequency.
固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。
Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.
不接受带有参考线频率的时钟的系统。
Systems with line frequency referred clocks not acceptable .
不接受带有参考线频率的时钟的系统。
同时给出了一种提高实时控制精度的有效方法，即通过改写系统定时器的分频值达到改变定时器时钟中断频率的值。
And it presents a efficacious method to enhance precision of real time control, which changes value of clock interrupt frequency by changing divided frequency of system tinier.
该结构可利用现有存储器件在不增加时钟频率的情况下，提高存储器系统的容量和速度，同时降低成本。
The capacity and speed of the memory subsystem in this architecture can be improved using the existed memory devices while the cost can be downgraded without enhancement of the clock frequency.
本文还给出了基于GPS芯片和CPLD，对系统压控晶振时钟进行校准的实现方法，有效解决了由于长时间使用，晶振自身特性变化，造成的频率偏移现象。
This paper introduces the method of clock calibration to VCXO in system, based on GPS and CPLD. It can solve the problem of frequency offset because of Crystal worse behavior in Long-term use.
因此，时钟频率直接影响单片机的速度，时钟电路的质量也直接影响单片机系统的稳定性。
Therefore, the clock frequency directly affect the speed of MCU, clocking circuit and the quality of directly influence the stability of single-chip microcomputer system.
随着采样频率和A/D变换器位数的增加，时钟抖动和相位噪声对数据采集系统性能的影响更加显著。
The effect of clock jitter and phase noise on data acquisition system performance is more profound as the increase of sampling frequency and the bit of A/D converter.
在数字系统中各个模块所需的时钟频率往往不相同，通常采用分频的方法由系统时钟得到所需频率。
Different components in a digital system often need different working frequencies, the way we often used is clock division from the system clock.
动态功耗管理是一种系统级低功耗设计技术，降低功耗的思路是根据系统当前负载动态调整时钟频率或者关闭时钟。
Dynamic power Management (DPM) is a technique to reduce power consumption of systems by shutting down clocks or changing their frequency according to system loads.
摘要：随着数字系统的工作频率的不断提高，时钟周期逐渐变小，而系统时序却越来越复杂。
Absrtact: Along with the increase of digital system working frequency, clock period gets shorter, timing of the system becomes more complex.
摘要：随着数字系统的工作频率的不断提高，时钟周期逐渐变小，而系统时序却越来越复杂。
Absrtact: Along with the increase of digital system working frequency, clock period gets shorter, timing of the system becomes more complex.
应用推荐