系统VCO模块采用微分电路设计技术，可将电源噪音对时钟信号输出抖动的影响降至最低。
The VCO module makes use of differential coefficient circuit design technology to lower the effect of power resource on the clock signal input shake.
固定频率源可以在在通讯系统和雷达系统中作为本机振荡器，也可以作为数字电路的基准时钟信号，因此得到了广泛的应用。
Single frequency source is usually used as local oscillator in communication system and radar system, also as a reference clock in digital circuits, so it is a extensive-applied technique.
这些功能的实现是通过系统中电控部分的电源、时钟、存储、超声波脉冲信号发生、处理、温度采集、串行通信电路实现的。
These functions are realized by the circuits of power, clock, memory, ultrasonic pulse signal occurs and handle, temperature gathered and serial communication in system.
设计了二进制树型拓扑结构传播统一的系统时钟和触发信号，采用CPLD提供传感器间的精确时序和同步。
A binary tree routing topology is designed for propagating the system clock and trigger signal and the accurate timing and synchronization between sensors are provided by CPLD.
该文提出了一种基于TDMA信号体制下的方波调制方案，该方案既解决了远近效应，又避免了在较高的中频上采用过高的系统时钟。
The paper presents a square wave modulation scheme based on TDMA signal system to resolve the problem. Also it can avoid the high speed system clock.
位同步时钟信号的提取是通信系统中的关键部分，应用数字锁相环可以准确地从输入码流中提取出位同步信号。
Bit synchronous clock recover circuit is the key part of the communication system, it can exactly recover the synchronous signal from input data stream.
为了实现水下载体高精度的定位，GPS声纳浮标需解决两个方面的技术难点：高精度的系统时钟同步和定位信号的高精度时延估计。
As for the high precision positioning of underwater targets, the GPS sonobuoy technique has two bottlenecks: high precision system clock synchronization and high accuracy time delay estimation.
时钟信号控制着数字系统的操作，它让逻辑门计算新的结果，然后由触发器存储执行结果。
Clock regulate the operation of a digital system by allowing time for new results to be calculated by logic gates and then capturing the results in flip-flops.
该系统采用了片同步技术实现了采样后高速数字信号的可靠锁存，采用高精度的时钟管理芯片和设计合理的时钟路径对时钟抖动做了严格控制。
The Chip-Sync technology has been used to ensure the latch of high-speed signal, and we use high accuracy clock management chips and design reasonable clock way to strict control the clock jitter.
通过FPGA实现在一定系统时钟和触发信号作用下各种工作模式的触发信号的产生。
Based on the system clock and trigger input signals, using FPGA to generate trigger output signals in given working modes.
数据采集系统包括信号调理电路、DSK接口电路、RS- 485通信接口电路、系统时钟电路及电源电路等。
The data acquisition system consists of the signal conditioning circuit, DSK interfacing circuit, RS-485 communication interfacing circuit, system clock circuit, the power circuit, and so on.
水下武器系统综合检测系统采用模块化设计思想，由信号发生器模块、A/D模块、D/A模块、实时时钟模块、液晶及打印机模块等组成。
The synthesized test system for underwater weapon system adopts a modularized structure with signal generator, A/D converter, D/A converter, real-time clock, printer and LCD screen.
本控制系统以高性能8位单片机at89c52为核心，结合数据采集电路、信号输出电路、实时时钟电路、系统监控电路组成。
The control system is composed of AT89C52, a high-powered 8-bit microcontroller, data gathering circuit, real time circuit, data output circuit and system watch circuit.
GPS同步时钟信号已在电力系统的继电保护、事件顺序记录、故障测距、同步采样等诸多领域获得重要运用。
The clock signal provided by Global Positioning System(GPS)is widely used in electric power system for relay protection, SOE (Sequence of Events), fault locating, synchronous sampling and so on.
在设计中整个系统采用了一个基准时钟源和同步源，并且各部分间的信号传输采用了有线的方式。
The fiducial clk and reset source of each part is same , and the information transmitted form part to part is on line.
该控制系统包括第一计数器，依据一提供的频道位时钟脉冲信号执行位计数；
The control system includes a first counter which performs a bit count according to provided channel bit clock signals;
通过对硬盘主轴马达的反电动势与马达转速之间关系的分析，提出一种利用马达的反电动势信号跟踪马达转动速度变化，产生系统伺服写入时钟信号的方法。
By analyzing relation between BEMF of the hard disk spindle motor and the rotate speed. This paper presents a new method of following the motor rotate speed by PLL to lock BEMF.
其中详细介绍时钟和帧定位信号传递的可靠性，同步系统可靠性以及数字信号连接等问题。
Emphasis is placed on the reliability of transmission of time clock and frame alignment signal, th...
其中详细介绍时钟和帧定位信号传递的可靠性，同步系统可靠性以及数字信号连接等问题。
Emphasis is placed on the reliability of transmission of time clock and frame alignment signal, th...
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