系统主芯片采用EP1K100 QC 208 - 3，由时钟模块、控制模块、计时模块、数据译码模块、显示以及报时模块组成。
The main system chips used EP1K100QC208-3, make up of the clock module, control module, time module, data decoding module, display and broadcast module.
理论及实例分析表明，通信系统的主—从时钟方式是电流差动保护装置在复用数字通信系统时正确工作的理想方式。
It is shown by theory and case study that the master - slave clock mode in a com munication system is ideal for proper functions of the current differential protection.
首先针对网络控制系统分布式的特点，特别是类似于CAN总线的多主系统，由于没有单一的时钟提供同步机制，影响调度管理的同步。
First, aiming at the distribution of NCS, specially the multi-master system such as CAN, there is no unified network clock, so the scheduling and management are affected.
论文还对通过建立主时钟实现总线系统同步通信机制进行了探讨，并给出了主时钟故障时防止系统崩溃的解决方案。
Meanwhile, the synchronizing communication realized by main clock is discussed, and the solution is brought forth to prevent system from breakdown due to main clock's fault.
该设备基于AT 89c51，采用软件抗干扰技术，实现授时主系统时钟与中心UT C主钟的同步。
Adopting software anti-jamming technology, this instrument is based on AT89C51 to achieve the synchronization of the clock of time service system with UTC.
该设备基于AT 89c51，采用软件抗干扰技术，实现授时主系统时钟与中心UT C主钟的同步。
Adopting software anti-jamming technology, this instrument is based on AT89C51 to achieve the synchronization of the clock of time service system with UTC.
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