本算法可直接结合到现有的RTL和门级网表的验证流程中,从而提高算术电路的验证能力。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
本算法可直接结合到现有的RTL和门级网表的验证流程中,从而提高算术电路的验证能力。
The approach can be easily incorporated into existing RTL to gate equivalence checking frameworks and increase the robustness of equivalence checking for arithmetic circuits.
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