如果等价性检查失败，检查器会生成一个输入向量序列，它可以在仿真中使用以便演示两个电路之间的差异。
If an equivalence check fails, the checker generates an input sequence of vectors that, when simulated, demonstrates the differences between the two circuits.
毫无疑问，两个电路在该输入序列下是不等价的。
Surely these two circuits are not equivalent under this input sequence.
通过利用抽取滤波器的等价变换和多项分解性质，各滤波器级的硬件电路开销和运行功耗都得到了降低。
By utilizing equivalent transformation and polyphase decomposition of the decimation filter, both hardware cost and operating power of each sub-decimation filter were also reduced.
为了提高时序电路的等价性验证速度，提出一种改进的基于寄存器匹配的验证算法。
An improved algorithm based on register mapping is proposed to increase the speed of equivalence checking for sequential circuits.
讨论了基于二叉判决图（BDD）的组合电路等价性检验方法，并分析了等价性检验过程中的误判问题及其消除方法；
The combinational equivalence checking methods based on binary decision diagram(BDD)are dis-cussed, the false negative problem during equivalence checking and its eliminating methods are analyzed.
提出一种基于状态转换图的时序电路等价验证算法。
A sequential equivalence checking algorithm based on state transfer graph is presented.
并讨论了基于递归学习的组合电路等价性检验方法；
The combinational equivalence check methods based on recursive learning algorithm are discussed.
并讨论了基于递归学习的组合电路等价性检验方法；
The combinational equivalence check methods based on recursive learning algorithm are discussed.
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