给出了系统硬件结构，对以内部硬件乘法器为FFT处理核的谐波分析技术进行了详细分析。
The harmonic analysis with the FFT processing nucleus based on the internal hardware multiplier is analyzed in detail.
DSP内部采用程序和数据分开的哈佛结构，具有专门的硬件乘法器，可以用来快速地实现各种数字信号处理算法。
DSP adopts Harvard structure in which program memory and data memory are divided. DSP can realize various digital signal process algorithms by special hardware multiplier.
数字信号处理(dsp)具有并行的硬件乘法器、流水线结构以及快速的片内存储器等资源，其技术广泛地应用于数字信号处理的各个领域。
DSP technologies have applied in every field of digital signal processing because of its parallel multiplier, pipeline structure and fast On-Chip memory.
说明了对偶基比特并行乘法器在硬件规模上的优越性。
The advantage of dual basis bit parallel multiplier in terms of the scale of hardware is explained.
利用双平衡模拟乘法器芯片MC1596，设计了正交复用方案的收发终端，并完成了终端的硬件的具体实现。
Using the MC1596, a monolithic balanced modulator circuit, to design the transmitting and receiving terminal, and complete the realization of the terminal hardwire.
新的乘法器采用比特串行方式，使得硬件结构更加规则，减少了原有乘法器关键路径的延迟。
The multiplier in this paper is Bit-serial mode and the new hardware architecture is regular which reduces the delay of the critical path.
乘法器是数字信号处理和媒体处理中应用最多，硬件面积最大的执行部件。
Multiplier is one of the most important units used in DSP and multimedia data processing.
使用不同方法，在FPGA上实现了多种乘法器结构的硬件描述，并给出了这些方法的优缺点和适用范围。
The work mainly as follow:(1) Use different method to implement many kinds of multiplication in FPGA, and list their advantages, disadvantages and suitable situation.
使用不同方法，在FPGA上实现了多种乘法器结构的硬件描述，并给出了这些方法的优缺点和适用范围。
The work mainly as follow:(1) Use different method to implement many kinds of multiplication in FPGA, and list their advantages, disadvantages and suitable situation.
应用推荐